Abstract: A display device includes a substrate including an emission area and a non-emission area, alignment electrodes arranged to be spaced from each other in a first direction on the substrate and extending in a second direction crossing the first direction, and pixels arranged along the second direction. Pixels adjacent to each other in the second direction from among the pixels may be configured to emit light of different colors. Each of the pixels may include first light emitting elements on the alignment electrodes and arranged along the second direction, second light emitting elements on the alignment electrodes, spaced from the first light emitting elements in the first direction, and arranged along the second direction, a first pixel electrode electrically connected to a first driving power and first ends of the first light emitting elements, a second pixel electrode spaced from the first pixel electrode in the first direction.

Abstract: A display device may include pixels on a substrate. Each of the pixels may include: a first alignment electrode and a second alignment electrode located on the substrate and spaced from each other; a first insulating layer on the first alignment electrode and the second alignment electrode; a light emitting element located on the first insulating layer between the first and second alignment electrodes; a dummy pattern located between the first insulating layer and the light emitting element; a second insulating layer located on the light emitting element and exposing first and second ends of the light emitting element; a first electrode electrically connected to the first end of the light emitting element; and a second electrode spaced from the first electrode, and electrically connected to the second end of the light emitting element. The dummy pattern may include a same material as the second insulating layer.

Abstract: A display device includes: light emitting elements, each of the light emitting elements including a first end having a first polarity and a second end having a second polarity different from the first polarity; and a first type connection electrode contacting the first ends and/or the second ends of the light emitting elements, wherein a first type connection electrode includes: a middle portion extending in a first direction; a first electrode portion extending from the middle portion toward a first side in a second direction intersecting the first direction; a second electrode portion extending from the middle portion toward the first side in the second direction and spaced from the first electrode portion by a first width in the first direction; a third electrode portion extending from the middle portion toward a second side in the second direction; and a fourth electrode portion.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

Abstract: A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.

Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

Abstract: A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.

Abstract: A semiconductor package includes a semiconductor chip mounted on a substrate that has a top surface and a bottom surface opposite to each other, and connection members that connect the substrate and the semiconductor chip to each other. The connection members include first connection members disposed on a central region of the semiconductor chip and that have heights equal to each other, and second connection members disposed on an edge region of the semiconductor chip and that have heights equal to each other. The heights of the first connection members differ from the heights of the second connection members.

Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

Abstract: Provided are a semiconductor chip and a semiconductor package capable of obtaining stability and reliability through a connection structure using a through-silicon-via (TSV). The semiconductor chip includes a semiconductor substrate and a through-silicon-via (TSV) structure penetrating through the semiconductor substrate. A connection pad includes a foundation base disposed on a lower surface of the semiconductor substrate and connected to the TSV structure. A protruding portion protrudes from the foundation base and extend to an inside of a first groove formed in a lower surface of the semiconductor substrate.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: An integrated circuit device is provided as follows. A connection terminal is disposed on a first surface of a semiconductor structure. A conductive pad is disposed on a second surface, opposite to the first surface, of the semiconductor structure. A through-substrate-via (TSV) structure penetrates through the semiconductor structure. An end portion of the TSV structure extends beyond the second surface of the semiconductor structure. The conductive pad surrounds the end portion of the TSV structure.

Abstract: A semiconductor package includes a package board that includes an circuit pattern and a plurality of contact pads electrically connected to the circuit pattern; a semiconductor chip having a plurality of chip pads; and a bump structure including a plurality of connecting bumps electrically connected with the semiconductor chip and the circuit pattern and a plurality of gap adjusting bumps bonded to the semiconductor chip and shaped into a slender bar between the semiconductor chip and the package board, the gap adjusting bumps spacing the semiconductor chip from the package board such that a gap space, S, is maintained between the package board and the semiconductor chip. A method of fabrication and a memory unit are disclosed.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.