Abstract: A substrate processing method is provided. The substrate processing method comprises loading a substrate onto a substrate support inside a chamber, forming a plasma inside the chamber, providing a first DC pulse signal to an electromagnet that generates a magnetic field inside the chamber and processing the substrate with the plasma, wherein the first DC pulse signal is repeated at a first period including a first section and a second section subsequent to the first section, the first DC pulse signal has a first level during the first section, and the first DC pulse signal has a second level different from the first level during the second section.

Abstract: The semiconductor chip package includes a package body with a recess and a plurality of barrier parts formed along one side thereof. Each of the barrier parts has a first region and a second region projecting from the first region, and adjacent first regions are separated by a slot. A semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, is disposed in the recess of the package body. A conductive member is disposed in each slot, and a connecting member, associated with each bonding pad, electrically connects the associated bonding pad with a corresponding conductive member. A sealing member seals the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members. Stacking these packages in the transverse and/or longitudinal direction further reduces their mounting area and increases the integrated capacity per unit of mounting area.

Abstract: A method of forming a semiconductor package that includes at least one structure having a central hole formed at a center portion of the structure, a plurality of outer holes around the center hole, and a plurality of conductor pieces buried in the outer holes; at least one TAB having lead lines extending from sides of the TAB, the TAB having a configuration substantially corresponding to the central hole of the structure and formed over the central hole of the structure; and a molding material covering at least a portion of the TAB.

Abstract: The semiconductor chip package includes a package body with a recess and a plurality of barrier parts formed along one side thereof. Each of the barrier parts has a first region and a second region projecting from the first region, and adjacent first regions are separated by a slot. A semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, is disposed in the recess of the package body. A conductive member is disposed in each slot, and a connecting member, associated with each bonding pad, electrically connects the associated bonding pad with a corresponding conductive member. A sealing member seals the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members. Stacking these packages in the transverse and/or longitudinal direction further reduces their mounting area and increases the integrated capacity per unit of mounting area.

Abstract: A semiconductor package includes at least one structure having a central hole formed at a center portion of the structure, a plurality of outer holes around the center hole, and a plurality of conductor pieces buried in the outer holes; at least one TAB having lead lines extending from sides of the TAB, the TAB having a configuration substantially corresponding to the central hole of the structure and formed over the central hole of the structure; and a molding material covering at least a portion of the TAB.