Abstract: A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feedback path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator.

Abstract: An apparatus and method for local oscillator calibration compensates for filter passband variation in a mixer circuit, such as a receiver circuit. The receiver includes at least a mixer circuit and a filter coupled to the output of the mixer. During operation, the mixer mixes an RF input signal with a first local oscillator (LO) signal to frequency translate a selected channel in the RF input signal into the passband of the filter. During a calibration mode, the RF input signal is disabled, and the first LO signal is injected into the filter input by leaking the first LO signal through the mixer circuit. The frequency of the LO signal is then swept over a frequency bandwidth that is sufficiently wide so that the actual passband is detected by measuring the signal amplitude at the output of the bandpass filter, thereby determining any variation in the passband of the filter from the expected passband.

Abstract: A dual conversion receiver selects and down-converts one channel from a plurality of channels in a received RF signal. The dual conversion receiver includes first and second mixer stages that are driven by first and second local oscillator signals. Channel selection is performed by tuning the first local oscillator signal so that a desired channel is up-converted to a first IF frequency, which defines the center of the passband of a first bandpass filter connected between the first and second mixer stages. The second mixer stage down-converts the output of the first bandpass filter to a second IF frequency, which is further filtered by a second bandpass filter. The first and second local oscillators can produce harmonics that mix in the second mixer stage, causing unwanted spurious signals that can fall in band with the second IF frequency.

Abstract: An apparatus and method for local oscillator calibration compensates for filter passband variation in a mixer circuit, such as a receiver circuit. The receiver includes at least a mixer circuit and a filter coupled to the output of the mixer. During operation, the mixer mixes an RF input signal with a first local oscillator (LO) signal to frequency translate a selected channel in the RF input signal into the passband of the filter. During a calibration mode, the RF input signal is disabled, and the first LO signal is injected into the filter input by leaking the first LO signal through the mixer circuit. The frequency of the LO signal is then swept over a frequency bandwidth that is sufficiently wide so that the actual passband is detected by measuring the signal amplitude at the output of the bandpass filter, thereby determining any variation in the passband of the filter from the expected passband.

Abstract: A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted noise at or near 0 Hz. The DC compensation is performed using direct coupling, as opposed to AC coupling, so that no useful signal information in the active period of the input signal is lost at DC. The DC compensation circuit samples the input signal during an inactive period of the input signal. Afterwhich, the unwanted DC noise is determined from the sampled signal and stored until an active period of the input signal. For example, the sampled signal can be filtered using a passband around DC so as to isolate the signal energy at DC during the inactive period. Since there is no useful signal information present during the inactive period, any signal energy at the output of the filter is necessarily unwanted DC noise.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: An apparatus and method for local oscillator calibration compensates for filter passband variation in a mixer circuit, such as a receiver circuit. The receiver includes at least a mixer circuit and a filter coupled to the output of the mixer. During operation, the mixer mixes an RF input signal with a first local oscillator (LO) signal to frequency translate a selected channel in the RF input signal into the passband of the filter. During a calibration mode, the RF input signal is disabled, and the first LO signal is injected into the filter input by leaking the first LO signal through the mixer circuit. The frequency of the LO signal is then swept over a frequency bandwidth that is sufficiently wide so that the actual passband is detected by measuring the signal amplitude at the output of the bandpass filter, thereby determining any variation in the passband of the filter from the expected passband.

Abstract: An apparatus and method for local oscillator calibration compensates for filter passband variation in a mixer circuit, such as a receiver circuit. The receiver includes at least a mixer circuit and a filter coupled to the output of the mixer. During operation, the mixer mixes an RF input signal with a first local oscillator (LO) signal to frequency translate a selected channel in the RF input signal into the passband of the filter. During a calibration mode, the RF input signal is disabled, and the first LO signal is injected into the filter input by leaking the first LO signal through the mixer circuit. The frequency of the LO signal is then swept over a frequency bandwidth that is sufficiently wide so that the actual passband is detected by measuring the signal amplitude at the output of the bandpass filter, thereby determining any variation in the passband of the filter from the expected passband.

Abstract: A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

Abstract: A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted noise at or near 0 Hz. The DC compensation is performed using direct coupling, as opposed to AC coupling, so that no useful signal information in the active period of the input signal is lost at DC. The DC compensation circuit samples the input signal during an inactive period of the input signal. Afterwhich, the unwanted DC noise is determined from the sampled signal and stored until an active period of the input signal. For example, the sampled signal can be filtered using a passband around DC so as to isolate the signal energy at DC during the inactive period. Since there is no useful signal information present during the inactive period, any signal energy at the output of the filter is necessarily unwanted DC noise.

Abstract: A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted noise at or near 0 Hz. The DC compensation is performed using direct coupling, as opposed to AC coupling, so that no useful signal information in the active period of the input signal is lost at DC. The DC compensation circuit samples the input signal during an inactive period of the input signal. Afterwhich, the unwanted DC noise is determined from the sampled signal and stored until an active period of the input signal. For example, the sampled signal can be filtered using a passband around DC so as to isolate the signal energy at DC during the inactive period. Since there is no useful signal information present during the inactive period, any signal energy at the output of the filter is necessarily unwanted DC noise.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low passn filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word.

Abstract: An integrated communications system. A substrate having a receiver disposed on the substrate for converting a received signal to an IF signal, a digital IF demodulator disposed on the substrate and coupled to the receiver for converting the IF signal to a demodulated baseband signal, and a transmitter disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.