Patents by Inventor Myoung-Hee Han
Myoung-Hee Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8071469Abstract: A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that are exposed through a monitoring window.Type: GrantFiled: July 19, 2010Date of Patent: December 6, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Myoung-Hee Han
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Publication number: 20100279500Abstract: A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that are exposed through a monitoring window.Type: ApplicationFiled: July 19, 2010Publication date: November 4, 2010Inventor: MYOUNG-HEE HAN
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Patent number: 7763887Abstract: A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that are exposed through a monitoring window.Type: GrantFiled: September 4, 2007Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Myoung-Hee Han
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Patent number: 7679161Abstract: In an embodiment, a semiconductor device includes a first fuse cutting portion in which fuse lines are arranged transversely adjacent to each other, a first runner portion in which runner lines connected to the fuse lines are arranged transversely adjacent to each other but at smaller intervals than those of the fuse lines, and a first connection portion having connection lines between the fuse lines and the runner lines. An insulating barrier layer covers the connection portions so that post-process residues from fuse cutting do not cause electrical shorts between the closely formed runner lines.Type: GrantFiled: October 25, 2006Date of Patent: March 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-Hee Han, Jong-Seop Lee
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Patent number: 7514736Abstract: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate having a memory cell array region and a peripheral region, a plurality of capacitors in the memory cell array region each having a storage electrode, a dielectric layer on the storage electrode, and a plate electrode on the dielectric layer, wherein an extended portion of the plate electrode extends in a direction toward the peripheral region, a dummy pattern in the peripheral region at an elevation above the semiconductor substrate that is substantially the same as that of the extended portion of the plate electrode and spaced apart from the extended portion of the plate electrode, an insulating layer formed on the plurality of capacitors in the cell array region and formed on the dummy pattern in the peripheral region, a first metal contact through the insulating layer between the extended portion of the plate electrode and the dummy pattern.Type: GrantFiled: June 5, 2006Date of Patent: April 7, 2009Assignee: Samsung Electronics Co., LtdInventors: Sung-hun Hong, Myoung-hee Han, Jong-seop Lee
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Publication number: 20080054263Abstract: A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that are exposed through a monitoring window.Type: ApplicationFiled: September 4, 2007Publication date: March 6, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Myoung-Hee HAN
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Publication number: 20070096251Abstract: In an embodiment, a semiconductor device includes a first fuse cutting portion in which fuse lines are arranged transversely adjacent to each other, a first runner portion in which runner lines connected to the fuse lines are arranged transversely adjacent to each other but at smaller intervals than those of the fuse lines, and a first connection portion having connection lines between the fuse lines and the runner lines. An insulating barrier layer covers the connection portions so that post-process residues from fuse cutting do not cause electrical shorts between the closely formed runner lines.Type: ApplicationFiled: October 25, 2006Publication date: May 3, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myoung-Hee HAN, Jong-Seop LEE
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Publication number: 20060284232Abstract: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate having a memory cell array region and a peripheral region, a plurality of capacitors in the memory cell array region each having a storage electrode, a dielectric layer on the storage electrode, and a plate electrode on the dielectric layer, wherein an extended portion of the plate electrode extends in a direction toward the peripheral region, a dummy pattern in the peripheral region at an elevation above the semiconductor substrate that is substantially the same as that of the extended portion of the plate electrode and spaced apart from the extended portion of the plate electrode, an insulating layer formed on the plurality of capacitors in the cell array region and formed on the dummy pattern in the peripheral region, a first metal contact through the insulating layer between the extended portion of the plate electrode and the dummy pattern.Type: ApplicationFiled: June 5, 2006Publication date: December 21, 2006Inventors: Sung-hun Hong, Myoung-hee Han, Jong-seop Lee
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Publication number: 20060255391Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: ApplicationFiled: July 24, 2006Publication date: November 16, 2006Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Beom KIM, Won-Mo PARK, Yun-Jae LEE, Joon-Mo KWON, Myoung-Hee HAN, Man-Jong YU
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Patent number: 7101769Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: GrantFiled: February 10, 2004Date of Patent: September 5, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Beom Kim, Won-Mo Park, Yun-Jae Lee, Joon-Mo Kwon, Myoung-Hee Han, Man-Jong Yu
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Publication number: 20040159909Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: ApplicationFiled: February 10, 2004Publication date: August 19, 2004Inventors: Seung-Beom Kim, Won-Mo Park, Yun-Jae Lee, Joon-Mo Kwon, Myoung-Hee Han, Man-Jong Yu
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Patent number: 6563162Abstract: A semiconductor memory device for reducing parasitic bit line capacitance and a method of fabricating the same are provided. The semiconductor memory device includes a conductive pad formed on a semiconductor substrate and a first interlayer insulating layer having a first contact hole that exposes the conductive pad. The first interlayer insulating layer is formed on the conductive pad and the semiconductor substrate. Bit line stacks are formed on the first interlayer insulating layer. Bit line spacers are formed from a combination of materials having different dielectric constants on the sidewalls of the bit line stack to reduce the parasitic bit line capacitance. Preferably, the bit line spacers are stack layers including silicon nitride, silicon oxide, and silicon nitride. A second interlayer insulating layer having a second contact hole is formed on the bit line stack. A conductive plug fills the first and second contact holes.Type: GrantFiled: March 19, 2002Date of Patent: May 13, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-Hee Han, Young-Hoon Park, Ju-Wan Kim, Ju-Bum Lee
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Patent number: 6555450Abstract: A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when a spacer of a NMOS transistor region is formed. And at the same time a gate capping insulating layer of the cell array region, the active region of the NMOS transistor and the gate node contact region remains at a predetermined thickness by etching the spacer. And then, by performing an ion implantation procedure on the entire surface, the direct pad polysilicon layer and the buried pad polysilicon layer are simultaneously ion-implanted.Type: GrantFiled: October 4, 2001Date of Patent: April 29, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hoon Park, Jin-Hun Lee, Myoung-Hee Han, Hyo-Dong Ban, Eun-Young Min, Won-Hee Jang
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Patent number: 6509255Abstract: A fuse area structure in a semiconductor device and a method of forming the same are provided. A ring-shaped guard ring which surrounds a fuse opening, for preventing moisture from seeping into the side surface of the exposed fuse opening, is included. The guard ring is integrally formed with a passivation film. In order to form the guard ring, a guard ring opening etching stop film is formed on a fuse line. A guard ring opening is formed using the etching stop film, and a contact hole is formed in a peripheral circuit. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the guard ring opening are formed. The conductive material layer formed on the guard ring opening is removed. The exposed etching stop film is removed. Finally, a passivation film is deposited on the entire surface of the resulting structure.Type: GrantFiled: August 23, 2001Date of Patent: January 21, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-young Minn, Young-hoon Park, Chi-hoon Lee, Myoung-hee Han
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Patent number: 6507086Abstract: A fuse area structure in a semiconductor device and a method of forming the same are provided. A ring-shaped guard ring which surrounds a fuse opening, for preventing moisture from seeping into the side surface of the exposed fuse opening, is included. The guard ring is integrally formed with a passivation film. In order to form the guard ring, a guard ring opening etching stop film is formed on a fuse line. A guard ring opening is formed using the etching stop film, and a contact hole is formed in a peripheral circuit. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the guard ring opening are formed. The conductive material layer formed on the guard ring opening is removed. The exposed etching stop film is removed. Finally, a passivation film is deposited on the entire surface of the resulting structure.Type: GrantFiled: November 17, 2000Date of Patent: January 14, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-young Minn, Young-hoon Park, Chi-hoon Lee, Myoung-hee Han
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Publication number: 20020135072Abstract: A semiconductor memory device for reducing parasitic bit line capacitance and a method of fabricating the same are provided. The semiconductor memory device includes a conductive pad formed on a semiconductor substrate and a first interlayer insulating layer having a first contact hole that exposes the conductive pad. The first interlayer insulating layer is formed on the conductive pad and the semiconductor substrate. Bit line stacks are formed on the first interlayer insulating layer. Bit line spacers are formed from a combination of materials having different dielectric constants on the sidewalls of the bit line stack to reduce the parasitic bit line capacitance. Preferably, the bit line spacers are stack layers including silicon nitride, silicon oxide, and silicon nitride. A second interlayer insulating layer having a second contact hole is formed on the bit line stack. A conductive plug fills the first and second contact holes.Type: ApplicationFiled: March 19, 2002Publication date: September 26, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Myoung-Hee Han, Young-Hoon Park, Ju-Wan Kim, Ju-Bum Lee
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Publication number: 20020068423Abstract: A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when a spacer of a NMOS transistor region is formed. And at the same time a gate capping insulating layer of the cell array region, the active region of the NMOS transistor and the gate node contact region remains at a predetermined thickness by etching the spacer. And then, by performing an ion implantation procedure on the entire surface, the direct pad polysilicon layer and the buried pad polysilicon layer are simultaneously ion-implanted.Type: ApplicationFiled: October 4, 2001Publication date: June 6, 2002Inventors: Young-Hoon Park, Jin-Hun Lee, Myoung-Hee Han, Hyo-Dong Ban, Eun-Young Min, Won-Hee Jang
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Publication number: 20010055848Abstract: A fuse area structure in a semiconductor device and a method of forming the same are provided. A ring-shaped guard ring which surrounds a fuse opening, for preventing moisture from seeping into the side surface of the exposed fuse opening, is included. The guard ring is integrally formed with a passivation film. In order to form the guard ring, a guard ring opening etching stop film is formed on a fuse line. A guard ring opening is formed using the etching stop film, and a contact hole is formed in a peripheral circuit. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the guard ring opening are formed. The conductive material layer formed on the guard ring opening is removed. The exposed etching stop film is removed. Finally, a passivation film is deposited on the entire surface of the resulting structure.Type: ApplicationFiled: August 23, 2001Publication date: December 27, 2001Inventors: Eun-Young Minn, Young-Hoon Park, Chi-Hoon Lee, Myoung-Hee Han