Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes an electrode plate applied with a power; an ion blocker positioned at a bottom side of the electrode plate, which has a plurality of top holes formed thereon, and which is grounded; a shower head positioned at a bottom side of the ion blocker and which has a plurality of bottom holes formed thereon; and a turbulence generating unit configured to have a turbulence space therein, and which is positioned at a space between the ion blocker and the shower head, and wherein the top hole is positioned to overlap the turbulence space when seen from above, and the bottom hole is positioned at an outer side of the turbulence space, and which faces at least one of a bottom surface of the ion blocker and an outer wall of the turbulence generating unit when seen from below.

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: a first variable resistance layer including antimony (Sb); a second variable resistance layer including antimony (Sb) with a content different from that of the first variable resistance layer, the second variable resistance layer having a crystallization speed different from that of the first variable resistance layer; and a first electrode interposed between the first variable resistance layer and the second variable resistance layer.

Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: a first variable resistance layer including antimony (Sb); a second variable resistance layer including antimony (Sb) with a content different from that of the first variable resistance layer, the second variable resistance layer having a crystallization speed different from that of the first variable resistance layer; and a first electrode interposed between the first variable resistance layer and the second variable resistance layer.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.

Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.

Abstract: A method for reading data of a memory cell including a resistive memory element having a low resistance state and a high resistance state according to stored data and a selection element may include applying a recovery voltage to both ends of the memory cell, and applying a read voltage to both ends of the memory cell and sensing the data. The recovery voltage may be equal to or more than a second voltage obtained by adding a drift value of the memory cell to a first voltage for turning on the memory cell in a case in which the resistive memory element is in the low resistance state.

Abstract: A method for reading a data of a memory cell comprising a selection device and a resistive memory device which has a high resistance state or a low resistance state according to a data stored therein includes: applying a first read voltage to the memory cell; applying a second read voltage to the memory cell, the second read voltage having a level lower than a level of the first read voltage; and sensing the data of the memory cell while the second read voltage is applied to the memory cell.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.

Abstract: An electronic device includes a semiconductor memory that includes: a memory cell coupled between first and second lines and having a specific resistance state; a first read circuit suitable for supplying a predetermined pattern of a read voltage to the first line to generate a cell current corresponding to the specific resistance state of the memory cell during a read operation mode; and a second read circuit suitable for generating read data based on the cell current flowing through the second line during the read operation mode.