Abstract: Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in each array cell or bitcell. For example, one or more memory cells may be converted to provide passive write assist to a plurality of other memory cells. As another example, each memory cell may independently implement passive write assist using one or more high resistive contacts to couple to the array power supply, resulting in the array voltage level being changed by different amounts in different memory cells according to cell variations.

Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.

Abstract: In some aspects, the disclosure is directed to methods and systems for sense reference generation. A first array and a second array of MTJ based cells are configured as a magnetoresistive random access memory block. The first array is matched to the second array, the first array and the second array each including rows of MTJ based cells for storing data bits. Responsive to a first row of MTJ based cells in the first array being selected for at least a first stored data bit to be read, a reference row of MTJ based cells in the second array is connected to at least a first comparator of a plurality of comparators via reference lines, to provide sense reference for determining a value of the first stored data bit. The reference lines are shorted together prior to connecting to a first input of the first comparator.

Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.

Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.

Abstract: Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in each array cell or bitcell. For example, one or more memory cells may be converted to provide passive write assist to a plurality of other memory cells. As another example, each memory cell may independently implement passive write assist using one or more high resistive contacts to couple to the array power supply, resulting in the array voltage level being changed by different amounts in different memory cells according to cell variations.

Abstract: Methods and systems that extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements are provided. Accordingly, significantly reduced area requirements and control circuitry complexity of memory elements is enabled. The provided methods and systems can be used in non-volatile memory storage, and are suitable for use in system on chip (SoC) products.

Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.

Abstract: According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading.

Abstract: Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip (SoC) products.

Abstract: Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.

Abstract: Multi-time programmable memory elements are disclosed. The disclosed memory elements extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmability. The disclosed memory elements significantly reduce area requirements and control circuitry complexity of memory elements. The disclosed memory elements can be used in non-volatile memory storage, and are suitable for use in system on chip (SoC) products.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading.

Abstract: Decoder circuits capable of decoding encoded ROM memory are provided. Embodiments provide several improvements over prior solutions which rely primarily on CMOS logic (e.g., inverters). For example, embodiments provide faster decoding by limiting the number of decoding stages to a single stage. Further, embodiments allow the use of partial swing (as opposed to full swing) on the bit lines, which results in significant power reduction. This, in turn, results in reduced amounts of capacitor discharges when reading the data.

Abstract: Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip (SoC) products.

Abstract: A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states.

Abstract: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.