Patents by Inventor Mysore S. Srinivas
Mysore S. Srinivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11221884Abstract: According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes assigning to a first set of virtual resources associated with a virtual machine a first priority and assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority. An operating system of the virtual machine is provided with the first and second priorities assigned to the respective first and second sets of virtual resources. The operating system dispatches to process a workload the virtual resources from the first set before dispatching the virtual resources from the second set.Type: GrantFiled: October 25, 2018Date of Patent: January 11, 2022Assignee: International Business Machines CorporationInventors: Vaijayanthimala K. Anand, Wen-Tzer T. Chen, William A. Maron, Mysore S. Srinivas, Basu Vaidyanathan
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Patent number: 10310860Abstract: A system and method adjust instruction dispatch in a multi-pipeline processor core having a plurality of execution units for improved performance of out-of-order execution of instructions. A dispatch adjust circuit receives a queue full signal from one or more of the execution queues that indicates the corresponding execution queue is full. In response to the queue full signal, the instruction dispatch circuit sends a stop signal to the instruction issuer to stop issuing additional instructions to the queues until one or more of the queues are empty. The dispatch adjust circuit may also receive a queue empty signal from the queues to detect when they are empty to send a start signal to the issuer.Type: GrantFiled: July 29, 2016Date of Patent: June 4, 2019Assignee: International Business Machines CorporationInventors: Wen-Tzer T. Chen, Diane G. Flemming, Sandy K. Kao, William A. Maron, Mysore S. Srinivas, Donald R. Stence, Calvin L. Sze
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Publication number: 20190065280Abstract: According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes assigning to a first set of virtual resources associated with a virtual machine a first priority and assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority. An operating system of the virtual machine is provided with the first and second priorities assigned to the respective first and second sets of virtual resources. The operating system dispatches to process a workload the virtual resources from the first set before dispatching the virtual resources from the second set.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Inventors: Vaijayanthimala K. Anand, Wen-Tzer T. Chen, William A. Maron, Mysore S. Srinivas, Basu Vaidyanathan
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Patent number: 10120726Abstract: According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources.Type: GrantFiled: November 23, 2015Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vaijayanthimala K. Anand, Wen-Tzer T. Chen, William A. Maron, Mysore S. Srinivas, Basu Vaidyanathan
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Publication number: 20180032343Abstract: A system and method adjusts instruction dispatch in a multi-pipeline processor core having a plurality of execution units for improved performance of out-of-order execution of instructions. A dispatch adjust circuit receives a queue full signal from one or more the execution queues that indicates the execution queue is full. In response to the full queue signal, the instruction dispatch circuit sends a stop signal to the instruction issuer to stop issuing additional instructions to the queues until one or more of the queues are empty. The dispatch adjust circuit may also receive a queue empty signal from the queues to detect when they are empty to send a start signal to the issuer.Type: ApplicationFiled: July 29, 2016Publication date: February 1, 2018Inventors: Wen-Tzer T. Chen, Diane G. Flemming, Sandy K. Kao, William A. Maron, Mysore S. Srinivas, Donald R. Stence, Calvin L. Sze
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Publication number: 20170308468Abstract: A system and technique for cache line memory access includes a processor, a sectored cache, a memory, a memory controller, and logic. The logic is executable to, responsive to a miss in the cache of a sector address requested by the processor, request a cache line from the memory. The cache line request is divided into first and second cache subline requests. A determination is made as to which of the first and second cache subline requests corresponds to the requested sector address. Responsive to determining that the first cache subline request corresponds to the requested sector address, the first cache subline request is placed into a high priority queue of the memory controller and the second cache subline request is placed into a low priority queue of the memory controller. Requests from the high priority queue are serviced before requests from the low priority queue.Type: ApplicationFiled: July 7, 2017Publication date: October 26, 2017Inventors: Robert H. Bell, JR., Men-Chow Chiang, Hong L. Hua, Mysore S. Srinivas
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Patent number: 9727469Abstract: According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied.Type: GrantFiled: February 15, 2013Date of Patent: August 8, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Bell, Jr., Men-Chow Chiang, Hong L. Hua, Mysore S. Srinivas
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Publication number: 20170168832Abstract: Methods, apparatuses, and computer program products for instruction weighting for performance profiling in a group dispatch processor are described. In a particular embodiment, a post processing profiler retrieves an execution sample including an instruction address of a youngest instruction in a dispatch group that has completed execution in a group dispatch processor and a number of instructions in the dispatch group. In the particular embodiment, the post processing profiler identifies, based on the instruction address of the youngest instruction and the number of instructions in the dispatch group, all of the instructions that are in the dispatch group at the time that the dispatch group completes execution. In the particular embodiment, the post processing profiler applies within an execution profile, the result of the execution sample, equally to all of the identified instructions that are in the dispatch group.Type: ApplicationFiled: December 11, 2015Publication date: June 15, 2017Inventors: ALEXANDER E. MERICAS, MARIA L. PESANTEZ, MYSORE S. SRINIVAS
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Publication number: 20170168833Abstract: Methods, apparatuses, and computer program products for instruction weighting for performance profiling in a group dispatch processor are described. In a particular embodiment, a post processing profiler retrieves an execution sample including an instruction address of a youngest instruction in a dispatch group that has completed execution in a group dispatch processor and a number of instructions in the dispatch group. In the particular embodiment, the post processing profiler identifies, based on the instruction address of the youngest instruction and the number of instructions in the dispatch group, all of the instructions that are in the dispatch group at the time that the dispatch group completes execution. In the particular embodiment, the post processing profiler applies within an execution profile, the result of the execution sample, equally to all of the identified instructions that are in the dispatch group.Type: ApplicationFiled: February 16, 2016Publication date: June 15, 2017Inventors: ALEXANDER E. MERICAS, MARIA L. PESANTEZ, MYSORE S. SRINIVAS
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Patent number: 9626294Abstract: According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.Type: GrantFiled: October 3, 2012Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Bell, Jr., Men-Chow Chiang, Hong L. Hua, Mysore S. Srinivas
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Patent number: 9563559Abstract: Some embodiments of the inventive subject matter are directed to operations that include determining that an access request to a computer memory results in a cache miss. In some examples, the operations further include determining an amount of cache resources used to service additional cache misses that occurred within a period prior to the cache miss. Furthermore, in some examples, the operations further include servicing the access request to the computer memory based, at least in part, on the amount of the cache resources used to service the additional cache misses within the period prior to the cache miss.Type: GrantFiled: May 21, 2014Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Robert H. Bell, Jr., Hong L. Hua, William A. Maron, Mysore S. Srinivas
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Patent number: 9459922Abstract: A data processing system includes physical computing resources that include a plurality of processors. The plurality of processors include a first processor having a first processor type and a second processor having a second processor type that is different than the first processor type. The data processing system also includes a resource manager to assign portions of the physical computing resources to be used when executing logical partitions. The resource manager is configured to assign a first portion of the physical computing resources to a logical partition, to determine characteristics of the logical partition, the characteristics including a memory footprint characteristic, to assign a second portion of the physical computing resources based on the characteristics of the logical partition, and to dispatch the logical partition to execute using the second portion of the physical computing resources.Type: GrantFiled: September 15, 2015Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Patent number: 9323527Abstract: A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.Type: GrantFiled: October 15, 2010Date of Patent: April 26, 2016Assignee: International Business Machines CorporationInventors: Robert H. Bell, Jr., Hong L. Hua, Ram Raghavan, Mysore S. Srinivas
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Patent number: 9298458Abstract: A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.Type: GrantFiled: March 22, 2012Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Robert H. Bell, Jr., Hong L. Hua, Ram Raghavan, Mysore S. Srinivas
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Publication number: 20160085595Abstract: According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources.Type: ApplicationFiled: November 23, 2015Publication date: March 24, 2016Inventors: Vaijayanthimala K. Anand, Wen-Tzer T. Chen, William A. Maron, Mysore S. Srinivas, Basu Vaidyanathan
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Publication number: 20160019095Abstract: A data processing system includes physical computing resources that include a plurality of processors. The plurality of processors include a first processor having a first processor type and a second processor having a second processor type that is different than the first processor type. The data processing system also includes a resource manager to assign portions of the physical computing resources to be used when executing logical partitions. The resource manager is configured to assign a first portion of the physical computing resources to a logical partition, to determine characteristics of the logical partition, the characteristics including a memory footprint characteristic, to assign a second portion of the physical computing resources based on the characteristics of the logical partition, and to dispatch the logical partition to execute using the second portion of the physical computing resources.Type: ApplicationFiled: September 15, 2015Publication date: January 21, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Patent number: 9218190Abstract: According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources.Type: GrantFiled: February 24, 2013Date of Patent: December 22, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vaijayanthimala K. Anand, Wen-Tzer T. Chen, William A. Maron, Mysore S. Srinivas, Basu Vaidyanathan
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Patent number: 9135079Abstract: A data processing system includes physical computing resources that include a plurality of processors. The plurality of processors include a first processor having a first processor type and a second processor having a second processor type that is different than the first processor type. The data processing system also includes a resource manager to assign portions of the physical computing resources to be used when executing logical partitions. The resource manager is configured to assign a first portion of the physical computing resources to a logical partition, to determine characteristics of the logical partition, the characteristics including a memory footprint characteristic, to assign a second portion of the physical computing resources based on the characteristics of the logical partition, and to dispatch the logical partition to execute using the second portion of the physical computing resources.Type: GrantFiled: October 21, 2009Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Patent number: 9135080Abstract: A computer implemented method includes determining first characteristics of a first logical partition, the first characteristics including a memory footprint characteristic. The method includes assigning a first portion of a first set of physical computing resources to the first logical partition. The first set of physical computing resources includes a plurality of processors that includes a first processor having a first processor type and a second processor having a second processor type. The first portion includes the second processor. The method includes dispatching the first logical partition to execute using the first portion. The method includes creating a second logical partition that includes the second processor and assigning a second portion of the first set of physical computing resources to the second logical partition. The method includes dispatching the second logical partition to execute using the second portion.Type: GrantFiled: April 30, 2012Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Patent number: 9052932Abstract: A system and technique for hybrid virtual machine configuration management includes a processor and executable logic to: assign to a first set of virtual resources associated with a virtual machine a first priority, the first set associated with entitled resources for the virtual machine; assign to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; map the first set to a first physical resource of a pool of shared physical resources, the pool of shared physical resources allocatable to the first and second sets, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocate the first physical resource to the first set of virtual resources.Type: GrantFiled: December 17, 2012Date of Patent: June 9, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vaijayanthimala K. Anand, Wen-Tzer T. Chen, William A. Maron, Mysore S. Srinivas, Basu Vaidyanathan