Abstract: An embodiment of the invention provides a memory. The memory includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a memory cell array. The memory cell array has a plurality of memory cells disposed at the intersections of the word and bit lines to form a matrix of rows and columns, wherein each memory cell comprises a resistive memory device and a transistor. The source lines are each disposed between two word lines, wherein each source line is coupled to source terminals of the transistors. When a RESET operation is applied to a selected memory cell, the voltage level of the source line is pulled up to a first voltage level, and when another operation is applied to the selected memory cell, the source line is grounded.

Abstract: An embodiment of the invention provides a memory. The memory includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a memory cell array. The memory cell array has a plurality of memory cells disposed at the intersections of the word and bit lines to form a matrix of rows and columns, wherein each memory cell comprises a resistive memory device and a transistor. The source lines are each disposed between two word lines, wherein each source line is coupled to source terminals of the transistors. When a RESET operation is applied to a selected memory cell, the voltage level of the source line is pulled up to a first voltage level, and when another operation is applied to the selected memory cell, the source line is grounded.