Patents by Inventor Myung-Ho Bae
Myung-Ho Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983501Abstract: The present invention relates to an apparatus and method for automatically generating machine reading comprehension training data, and more particularly, to an apparatus and method for automatically generating and managing machine reading comprehension training data based on text semantic analysis. The apparatus for automatically generating machine reading comprehension training data according to the present invention includes a domain selection text collection unit configured to collect pieces of text data according to domains and subjects, a paragraph selection unit configured to select a paragraph using the pieces of collected text data and determine whether questions and correct answers are generatable, and a question and correct answer generation unit configured to generate questions and correct answers from the selected paragraph.Type: GrantFiled: October 7, 2021Date of Patent: May 14, 2024Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Yong Jin Bae, Joon Ho Lim, Min Ho Kim, Hyun Kim, Hyun Ki Kim, Ji Hee Ryu, Kyung Man Bae, Hyung Jik Lee, Soo Jong Lim, Myung Gil Jang, Mi Ran Choi, Jeong Heo
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Patent number: 11152056Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A true digit-line has a short first region along the first deck and a long second region along the second deck. A complementary digit-line has a long first region along the first deck and a short second region along the second deck. A first set of first memory cells is associated with the true digit-line. The first set includes a first subset along the short first region, a second subset along a portion of the long second region, and a third subset along another portion of the long second region. A routing region of the true digit-line extends between the second and third subsets of the first memory cells. A connection extends from the short first region to the routing region of the true digit-line.Type: GrantFiled: September 14, 2020Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Seung Yeong Seo, Myung Ho Bae
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Patent number: 11145354Abstract: An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output dock signal.Type: GrantFiled: March 11, 2021Date of Patent: October 12, 2021Assignee: Micron Technology, Inc.Inventors: Michael V. Ho, Myung Ho Bae
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Patent number: 11132142Abstract: A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.Type: GrantFiled: October 5, 2020Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Byung S. Moon, Harish N. Venkata, Gary L. Howe, Myung Ho Bae
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Patent number: 11087820Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.Type: GrantFiled: August 30, 2019Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: Yu-Feng Chen, Byung S. Moon, Myung Ho Bae, Harish N. Venkata
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Publication number: 20210201979Abstract: An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output dock signal.Type: ApplicationFiled: March 11, 2021Publication date: July 1, 2021Applicant: Micron Technology, Inc.Inventors: Michael V. Ho, Myung Ho Bae
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Patent number: 10950291Abstract: An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output clock signal.Type: GrantFiled: October 23, 2019Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Michael V. Ho, Myung Ho Bae
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Publication number: 20210019075Abstract: A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Byung S. Moon, Harish N. Venkata, Gary L. Howe, Myung Ho Bae
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Patent number: 10795603Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.Type: GrantFiled: August 29, 2019Date of Patent: October 6, 2020Assignee: Micron Technology, Inc.Inventors: Byung S. Moon, Harish N. Venkata, Gary L. Howe, Myung Ho Bae
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Patent number: 10606512Abstract: Methods and devices that receive commands at a command interface and uses control circuitry configured to implement the command. A routing pipeline is configured to translate and route the command from the command interface to the control circuitry. The routing pipeline includes clock circuitry. The clock circuitry includes a clock delay line and multiple cloned delay lines derived from the clock delay line. Each of the cloned delay lines are dedicated to a command type of multiple command types. The routing pipeline also includes delay circuitry configured to utilize the cloned delay lines to shift a data pin signal of the semiconductor device or shift a data strobe pin signal of the semiconductor device.Type: GrantFiled: October 23, 2017Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventors: Kallol Mazumder, Myung-Ho Bae
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Publication number: 20190392887Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.Type: ApplicationFiled: August 30, 2019Publication date: December 26, 2019Inventors: Yu-Feng Chen, Byung S. Moon, Myung Ho Bae, Harish N. Venkata
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Publication number: 20190384526Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Byung S. Moon, Harish N. Venkata, Gary L. Howe, Myung Ho Bae
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Patent number: 10497424Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.Type: GrantFiled: December 6, 2017Date of Patent: December 3, 2019Assignee: Micron Technology, Inc.Inventors: Yu-Feng Chen, Byung S. Moon, Myung Ho Bae, Harish N. Venkata
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Patent number: 10483970Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.Type: GrantFiled: November 26, 2018Date of Patent: November 19, 2019Assignee: Micron Technology, Inc.Inventors: Kallol Mazumder, Myung-Ho Bae
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Patent number: 10470475Abstract: A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.Type: GrantFiled: November 21, 2018Date of Patent: November 12, 2019Assignee: Micron Technology, Inc.Inventors: Kallol Mazumder, Myung-Ho Bae
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Patent number: 10402116Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.Type: GrantFiled: December 11, 2017Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Byung S. Moon, Harish N. Venkata, Gary L. Howe, Myung Ho Bae
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Publication number: 20190179560Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.Type: ApplicationFiled: December 11, 2017Publication date: June 13, 2019Inventors: Byung S. Moon, Harish N. Venkata, Gary L. Howe, Myung Ho Bae
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Publication number: 20190172518Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.Type: ApplicationFiled: December 6, 2017Publication date: June 6, 2019Inventors: Yu-Feng Chen, Byung S. Moon, Myung Ho Bae, Harish N. Venkata
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Publication number: 20190121577Abstract: Methods and devices that receive commands at a command interface and uses control circuitry configured to implement the command. A routing pipeline is configured to translate and route the command from the command interface to the control circuitry. The routing pipeline includes clock circuitry. The clock circuitry includes a clock delay line and multiple cloned delay lines derived from the clock delay line. Each of the cloned delay lines are dedicated to a command type of multiple command types. The routing pipeline also includes delay circuitry configured to utilize the cloned delay lines to shift a data pin signal of the semiconductor device or shift a data strobe pin signal of the semiconductor device.Type: ApplicationFiled: October 23, 2017Publication date: April 25, 2019Inventors: Kallol Mazumder, Myung-Ho Bae
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Publication number: 20190097630Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Inventors: Kallol Mazumder, Myung-Ho Bae