Patents by Inventor Myung Kwan Ryu

Myung Kwan Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11251259
    Abstract: An organic light-emitting diode display may have rounded corners. A negative power supply path may be used to distribute a negative voltage to a cathode layer, while a positive power supply path may be used to distribute a positive power supply voltage to each pixel in the display. The positive power supply path may have a cutout that is occupied by the negative power supply path to decrease resistance of the negative power supply path in a rounded corner of the display. To mitigate reflections caused by the positive power supply path being formed over tightly spaced data lines, the positive power supply path may be omitted in a rounded corner of the display, a shielding layer may be formed over the positive power supply path in the rounded corner, or non-linear gate lines may be formed over the positive power supply path.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 15, 2022
    Assignee: Apple Inc.
    Inventors: Tiffany T. Moy, Yuchi Che, Seonpil Jang, Warren S. Rieutort-Louis, Bhadrinarayana Lalgudi Visweswaran, Jae Won Choi, Abbas Jamshidi Roudbari, Myung-Kwan Ryu, Hirokazu Yamagata, Keisuke Otsu
  • Publication number: 20200357879
    Abstract: An organic light-emitting diode display may have rounded corners. A negative power supply path may be used to distribute a negative voltage to a cathode layer, while a positive power supply path may be used to distribute a positive power supply voltage to each pixel in the display. The positive power supply path may have a cutout that is occupied by the negative power supply path to decrease resistance of the negative power supply path in a rounded corner of the display. To mitigate reflections caused by the positive power supply path being formed over tightly spaced data lines, the positive power supply path may be omitted in a rounded corner of the display, a shielding layer may be formed over the positive power supply path in the rounded corner, or non-linear gate lines may be formed over the positive power supply path.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Tiffany T. Moy, Yuchi Che, Seonpil Jang, Warren S. Rieutort-Louis, Bhadrinarayana Lalgudi Visweswaran, Jae Won Choi, Abbas Jamshidi Roudbari, Myung-Kwan Ryu, Hirokazu Yamagata, Keisuke Otsu
  • Patent number: 10763323
    Abstract: An organic light-emitting diode display may have rounded corners. A negative power supply path may be used to distribute a negative voltage to a cathode layer, while a positive power supply path may be used to distribute a positive power supply voltage to each pixel in the display. The positive power supply path may have a cutout that is occupied by the negative power supply path to decrease resistance of the negative power supply path in a rounded corner of the display. To mitigate reflections caused by the positive power supply path being formed over tightly spaced data lines, the positive power supply path may be omitted in a rounded corner of the display, a shielding layer may be formed over the positive power supply path in the rounded corner, or non-linear gate lines may be formed over the positive power supply path.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 1, 2020
    Assignee: Apple Inc.
    Inventors: Tiffany T. Moy, Yuchi Che, Seonpil Jang, Warren S. Rieutort-Louis, Bhadrinarayana Lalgudi Visweswaran, Jae Won Choi, Abbas Jamshidi Roudbari, Myung-Kwan Ryu, Hirokazu Yamagata, Keisuke Otsu
  • Publication number: 20190393295
    Abstract: An organic light-emitting diode display may have rounded corners. A negative power supply path may be used to distribute a negative voltage to a cathode layer, while a positive power supply path may be used to distribute a positive power supply voltage to each pixel in the display. The positive power supply path may have a cutout that is occupied by the negative power supply path to decrease resistance of the negative power supply path in a rounded corner of the display. To mitigate reflections caused by the positive power supply path being formed over tightly spaced data lines, the positive power supply path may be omitted in a rounded corner of the display, a shielding layer may be formed over the positive power supply path in the rounded corner, or non-linear gate lines may be formed over the positive power supply path.
    Type: Application
    Filed: April 4, 2019
    Publication date: December 26, 2019
    Inventors: Tiffany T. Moy, Yuchi Che, Seonpil Jang, Warren S. Rieutort-Louis, Bhadrinarayana Lalgudi Visweswaran, Jae Won Choi, Abbas Jamshidi Roudbari, Myung-Kwan Ryu, Hirokazu Yamagata, Keisuke Otsu
  • Patent number: 9825066
    Abstract: A thin film transistor substrate includes a gate electrode, a channel layer overlapping the gate electrode, a source electrode overlapping the channel layer, a drain electrode overlapping the channel layer and the source electrode, and a spacer disposed between the source electrode and the drain electrode.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myung-Kwan Ryu, Eok-Su Kim, Kyoung Seok Son, Seung-Ha Choi, Sho-Yeon Kim, Hyun Kim, Eun-Hye Park, Byung-Hwan Chu
  • Patent number: 9755054
    Abstract: There are provided a method of manufacturing a thin film transistor and a display including a thin film transistor. The method of manufacturing a thin film transistor includes forming a barrier layer cm a substrate, forming a semiconductor layer on the barrier layer, forming a gate insulating layer on the semiconductor layer, forming a gate electrode on the gate insulating layer, forming an offset region on an external surface of the gate electrode through a plasma heat treatment process or an annealing process, etching, an offset region of the gate electrode, etching a gate insulating layer except for a portion of the gate insulating layer, positioned below the gate electrode, forming an interlayer insulating layer on the gate electrode, and etching, the interlayer insulating layer to form a source electrode and a drain electrode.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: September 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myung Kwan Ryu, Ki Hwan Kim, Kap Soo Yoon, Hyeon Jun Lee, Jeong Uk Heo
  • Patent number: 9660091
    Abstract: A thin film transistor (TFT) and a method of driving the same are disclosed. The TFT includes: an active layer; a bottom gate electrode disposed below the active layer to drive a first region of the active layer; and a top gate electrode disposed on the active layer to drive a second region of the active layer. The TFT controls the conductivity of the active layer by using the bottom gate electrode and the top gate electrode.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eok-su Kim, Myung-kwan Ryu, Kyoung-seok Son, Sung-hee Lee
  • Patent number: 9564531
    Abstract: Thin film transistors including a semiconductor channel disposed between a drain electrode and a source electrode; and a gate insulating layer disposed between the semiconductor channel and a gate electrode wherein the semiconductor channel includes a first metal oxide, the gate insulating layer includes a second metal oxide, and at least one metal of the second metal oxide is the same as at least one metal of the first metal oxide, methods of manufacturing thin film transistors, and semiconductor device including thin film transistors.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Bae Park, Myung-Kwan Ryu, Jong-Baek Seon, Sang-Yoon Lee, Bon-Won Koo
  • Publication number: 20160218197
    Abstract: There are provided a method of manufacturing a thin film transistor and a display including a thin film transistor. The method of manufacturing a thin film transistor includes forming a barrier layer cm a substrate, forming a semiconductor layer on the barrier layer, forming a gate insulating layer on the semiconductor layer, forming a gate electrode on the gate insulating layer, forming an offset region on an external surface of the gate electrode through a plasma heat treatment process or an annealing process, etching, an offset region of the gate electrode, etching a gate insulating layer except for a portion of the gate insulating layer, positioned below the gate electrode, forming an interlayer insulating layer on the gate electrode, and etching, the interlayer insulating layer to form a source electrode and a drain electrode.
    Type: Application
    Filed: December 1, 2015
    Publication date: July 28, 2016
    Inventors: Myung Kwan RYU, Ki Hwan KIM, Kap Soo YOON, Hyeon Jun LEE, Jeong Uk HEO
  • Publication number: 20160211281
    Abstract: A thin film transistor substrate includes a gate electrode, a channel layer overlapping the gate electrode, a source electrode overlapping the channel layer, a drain electrode overlapping the channel layer and the source electrode, and a spacer disposed between the source electrode and the drain electrode.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 21, 2016
    Inventors: Myung-Kwan Ryu, Eok-Su Kim, Kyoung Seok Son, Seung-Ha Choi, Sho-Yeon Kim, Hyun Kim, Eun-Hye Park, Byung-Hwan Chu
  • Patent number: 9384973
    Abstract: Provided are semiconductor films, methods of forming the same, transistors including the semiconductor films, and methods of manufacturing the transistors. Provided are a semiconductor film including zinc (Zn), nitrogen (N), oxygen (O), and fluorine (F), and a method of forming the semiconductor film. Provided are a semiconductor film including zinc, nitrogen, and fluorine, and a method of forming the semiconductor film. Sputtering, ion implantation, plasma treatment, chemical vapor deposition (CVD), or a solution process may be used in order to form the semiconductor films. The sputtering may be performed by using a zinc target and a reactive gas including fluorine. The reactive gas may include nitrogen and fluorine, or nitrogen, oxygen, and fluorine.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: July 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-sang Kim, Jong-baek Seon, Myung-kwan Ryu, Chil Hee Chung
  • Patent number: 9343534
    Abstract: According to example embodiments, a semiconductor material may include zinc, nitrogen, and fluorine. The semiconductor material may further include oxygen. The semiconductor material may include a compound. For example, the semiconductor material may include zinc fluorooxynitride. The semiconductor material may include zinc oxynitride containing fluorine. The semiconductor material may include zinc fluoronitride. The semiconductor material may be applied as a channel material of a thin film transistor (TFT).
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: May 17, 2016
    Assignees: Samsung Electronics Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Tae-sang Kim, Sun-jae Kim, Hyun-suk Kim, Myung-kwan Ryu, Joon-seok Park, Seok-jun Seo, Jong-baek Seon, Kyoung-seok Son
  • Patent number: 9312391
    Abstract: A solution composition for forming an oxide semiconductor includes a metal oxide precursor, and one of a metal thioacetate and a derivative thereof.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-baek Seon, Myung-kwan Ryu, Sang-yoon Lee
  • Patent number: 9245779
    Abstract: A method of preparing a thin film includes coating a thin film-forming composition on a substrate, and heat-treating the coated thin film-forming composition under a pressure less than 760 Torr. The thin film includes a compact layer having a thickness in a range of greater than 50 ? to about 20,000 ? and a refractive index in a range of about 1.85 to about 2.0.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: January 26, 2016
    Assignees: Samsung Electronics Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Myung-kwan Ryu, Jong-baek Seon, Sang-yoon Lee
  • Patent number: 9245957
    Abstract: According to example embodiments, a semiconductor material may include zinc, nitrogen, and fluorine. The semiconductor material may further include oxygen. The semiconductor material may include a compound. For example, the semiconductor material may include zinc fluorooxynitride. The semiconductor material may include zinc oxynitride containing fluorine. The semiconductor material may include zinc fluoronitride. The semiconductor material may be applied as a channel material of a thin film transistor (TFT).
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: January 26, 2016
    Assignees: Samsung Electronics Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Tae-sang Kim, Sun-jae Kim, Hyun-suk Kim, Myung-kwan Ryu, Joon-seok Park, Seok-jun Seo, Jong-baek Seon, Kyoung-seok Son
  • Patent number: 9184300
    Abstract: A transistor may include a hole blocking layer between a channel layer including oxynitride and an electrode electrically connected to the channel layer. The hole blocking layer may be disposed in a region between the channel layer and at least one of a source electrode and a drain electrode. The channel layer may include, for example, zinc oxynitride (ZnON). A valence band maximum energy level of the hole blocking layer may be lower than a valence band maximum energy level of the channel layer.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: November 10, 2015
    Assignees: Samsung Electronics Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Kyoung-seok Son, Myung-kwan Ryu, Tae-sang Kim, Hyun-suk Kim, Joon-seok Park, Jong-baek Seon, Sang-yoon Lee
  • Patent number: 9123750
    Abstract: According to example embodiments, a transistor may include a gate electrode, a gate insulating layer, and a channel layer stacked on each other; and a source electrode and a drain electrode contacting first and second regions of the channel layer, respectively. The channel layer may include metal oxynitride. The first and second regions of the channel layer may be treated with a plasma containing hydrogen, and the first and second regions have a higher carrier concentration than a carrier concentration of a remaining region of the channel layer. The first and second regions of the channel layer may have a lower oxygen concentration and a higher nitrogen concentration than that of the remaining region thereof. The metal oxynitride of the channel layer may include a zinc oxynitride (ZnON)-based semiconductor.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: September 1, 2015
    Assignees: Samsung Electronics Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Joon-seok Park, Sun-jae Kim, Tae-sang Kim, Hyun-suk Kim, Myung-kwan Ryu, Seok-jun Seo, Jong-baek Seon, Kyoung-seok Son, Sang-yoon Lee
  • Patent number: 9099561
    Abstract: A transistor may include a light-blocking layer that blocks light incident on a channel layer. The light-blocking layer may include a carbon-based material. The carbon-based material may include graphene oxide, graphite oxide, graphene or carbon nanotube (CNT). The light-blocking layer may be between a gate and at least one of the channel layer, a source and a drain.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: August 4, 2015
    Assignees: Samsung Electronics Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Hyun-suk Kim, Sang-yoon Lee, Myung-kwan Ryu, Tae-sang Kim, Jong-baek Seon, Kyoung-seok Son, Won-mook Choi, Joon-seok Park, Mi-jeong Song
  • Patent number: 9087907
    Abstract: According to example embodiments, a thin film transistor (TFT) includes a channel layer including zinc, nitrogen, and oxygen; an etch stop layer on the channel layer; source and drain electrodes respectively contacting both ends of the channel layer; a gate electrode corresponding to the channel layer; and a gate insulating layer between the channel layer and the gate electrode. The etch stop layer includes fluorine. The channel layer may be on the gate electrode.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: July 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-suk Kim, Sun-jae Kim, Tae-sang Kim, Myung-kwan Ryu, Joon-seok Park, Kyoung-seok Son
  • Patent number: 9076721
    Abstract: A transistor includes a channel layer including an oxynitride semiconductor doped with at least one of hafnium (Hf) and zirconium (Zr), a source on one side portion of the channel layer and a drain on another side portion of the channel layer, a gate corresponding to the channel layer, and a gate insulation layer between the channel layer and the gate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: July 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-seok Park, Sun-jae Kim, Tae-sang Kim, Hyun-suk Kim, Myung-kwan Ryu, Seok-jun Seo, Jong-baek Seon, Kyoung-seok Son, Sang-yoon Lee