Abstract: A cleaning kit for an aerosol generating device includes a power supplier; a cleaner configured to clean the aerosol generating device by moving while contacting at least one of an accommodation unit and a heater of the aerosol generating device, and a driver configured to operate the cleaner according to power from the power supplier, and including a gear unit for changing an operating torque of the cleaner.

Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.

Abstract: The present disclosure provides a mobile communications system line number sheet management device and method. Provided, according to one aspect of the present disclosure, is a line number sheet management device and method, for automating access network-related line number sheet management by automatically collecting and updating line number information, the line number information being collected from a mobile communications base station management server (mobile communications system management server) and a fronthaul management server. Provided, according to another aspect of the present disclosure, is a fronthaul device for: acquiring unique information of a base station by receiving an optical signal from any one of a radio unit (RU) and a digital unit (DU); and transmitting the unique information of the base station to a fronthaul management server.

Abstract: A window includes a window base layer, a high refractive layer disposed on the window base layer, a low refractive layer including hollow silica particles and disposed on the high refractive layer, and a primer coating layer disposed on the low refractive layer. Each of the low refractive layer and the primer coating layer has a refractive index in a range of about 1.4 to about 1.46. The low refractive layer has a thickness in a range of about 50 nm to about 80 nm.

Abstract: A power control device configured for diagnosing an open-circuit fault occurring in a power system of an autonomous vehicle and an open-circuit diagnosis method thereof, may include a power control switch that selectively connects or separates main power output from the first power supply and auxiliary power output from the second power supply, and a processor that determines a possibility of an open-circuit fault of a vehicle power source based on a current flowing through the power control switch and determines whether it is possible to drive an electric load with an output power of the second power supply alone and determine an open-circuit position based on an output of the first power supply when there is the possibility of the open-circuit fault.

Abstract: The present invention relates to a bee venom-purifying method comprising a virus clearance process and a composition for preventing or treating inflammatory disease by using same, the method comprising the steps of: (a) preparing a bee venom solution containing bee venom; (b) adjusting the pH of the bee venom solution prepared in step (a) into 2.0 to 4.0 by acid treatment to primarily deactivate viruses; and (c) filtering the pH-adjusted bee venom solution of step (b) through a nanofilter of 10 to 20 nm to secondarily remove viruses.

Abstract: Provided is a semiconductor device. A semiconductor device may include: a substrate formed to extend along a first direction; a first semiconductor chip formed on the substrate; a second semiconductor chip formed on the substrate at a predetermined distance from the first semiconductor chip along the first direction; a first lead frame extending outwardly beyond the substrate along the first direction, the first lead frame having a lower surface connected to upper surfaces of each of the first semiconductor chip and the second semiconductor chip; and a heat sink formed at a position corresponding to the first semiconductor chip and the second semiconductor chip on the first lead frame, wherein the first lead frame includes a first groove region formed between a region on the lower surface connected to the upper surface of the first semiconductor chip and a region on the lower surface connected to the upper surface of the second semiconductor chip.

Abstract: A semiconductor device includes an isolation structure having first and second sidewalls opposite each other, a first fin-shaped pattern in contact with the first sidewall and extending in the second direction, a second fin-shaped pattern in contact with the second sidewall and extending in the second direction, a first gate electrode on the first fin-shaped pattern, a first source/drain contact on the first and second fin-shaped patterns and extending between the first gate electrode and the element isolation structure, and a wiring structure on and connected to the first source/drain contact, wherein the first source/drain contact includes a lower contact intersecting the first and second fin-shaped patterns, an upper contact protruding from the lower contact, and a dummy contact, the wiring structure being in contact with the upper contact and not with the dummy contact.

Abstract: A power module package is provided. The power module package may include: a first substrate; a second substrate; a semiconductor chip disposed between the first substrate and the second substrate; and a mutual-connection layer that is formed between the semiconductor chip and the second substrate and provides conductive connection between the semiconductor chip and the second substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a gate electrode extending in a second direction intersecting the first direction on the active pattern, a gate spacer extending in the second direction along side walls of the gate electrode, an interlayer insulating layer contacting side walls of the gate spacer, a trench formed on the gate electrode in the interlayer insulating layer, a first capping pattern provided along side walls of the trench, at least one side wall of the first capping pattern having an inclined profile, and a second capping pattern provided on the first capping pattern in the trench.

Abstract: A storage device includes; a non-volatile memory, and a storage controller including a processor, an accelerator and a memory storing a flash translation layer including a mapping table including mapping information between logical page numbers and physical page numbers. The processor may provide a command to the non-volatile memory and provide first mapping update information in a first mapping update size to the accelerator. Upon updating mapping information of the mapping table, the accelerator may update mapping information for logical page numbers and check continuity for the first mapping update information.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising an element isolation region and an active region defined by the element isolation region, a fin-type pattern on the active region, the fin-type pattern extending in a first horizontal direction, a gate electrode on the fin-type pattern, the gate electrode extending in a second horizontal direction that crosses the first horizontal direction, a capping pattern on the gate electrode, a source/drain region on at least one side of the gate electrode, a source/drain contact on the source/drain region and electrically connected to the source/drain region, and a filling insulating layer on the source/drain contact, the filling insulating layer having a top surface at a same level as a top surface of the capping pattern, and including a material containing a carbon (C) atom.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: A semiconductor device is capable of improving the performance and reliability of a device. The semiconductor device includes a first fin-shaped pattern which extends lengthwise in a first direction, a second fin-shaped pattern which is spaced apart from the first fin-shaped pattern in a second direction and extends lengthwise in the first direction, a first gate electrode extending lengthwise in the second direction on the first fin-shaped pattern, a second gate electrode extending lengthwise in the second direction on the second fin-shaped pattern, a first gate separation structure which separates the first gate electrode and the second gate electrode and is at the same vertical level as the first gate electrode and the second gate electrode, and a first source/drain contact extending lengthwise in the second direction on the first fin-shaped pattern and the second fin-shaped pattern.

Abstract: A semiconductor device including a field insulating layer, a part of which protrudes upwardly in a vertical direction on an element isolation region between a first active region and a second active region may be provided. Accordingly, a depth of a source/drain contact to be provided may be reduced, thereby reducing difficulty for providing the source/drain contact may be reduced.

Abstract: A semiconductor device includes a substrate having a first power supply region, a second power supply region, and a cell region therein. The cell region extends between the first power supply region and the second power supply region. A first active region and a second active region are provided, which extend side-by-side within the cell region. A first power supply wiring is provided, which extends in the first direction within the first power supply region. A first source/drain contact is provided, which connects the first active region and the second active region. A second source/drain contact is provided, which connects the first active region and the first power supply wiring. The first source/drain contact includes a first recess portion disposed inside an intermediate region between the first active region and the second active region.

Abstract: A packaged power semiconductor device is provided. The packaged power semiconductor device may include: a direct bonded copper (DBC) substrate configured to include an upper surface in which an upper region, a middle region, and a lower region are defined; a metal tab formed to be directly connected to the upper surface in the upper region; a first lead formed to be directly connected to the upper surface in the lower region; and a semiconductor chip formed on the upper surface in the middle region.

Abstract: A semiconductor device includes an active pattern extending in a first direction on a substrate, a gate structure on the active pattern and having a gate electrode extending in a second direction intersecting the active pattern, and a gate capping pattern on the gate electrode, the gate capping pattern including a gate capping liner defining a gate capping recess, the gate capping liner having a horizontal portion along an upper surface of the gate electrode, and a vertical portion extending from the horizontal portion in a third direction intersecting the first and second directions, and a gate capping filling film on the gate capping liner and filling the gate capping recess, an epitaxial pattern on the active pattern and adjacent the gate structure, a gate contact on and connected to the gate electrode, and an active contact on and connected to the epitaxial pattern.