Patents by Inventor Myung Kil Lee
Myung Kil Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8816487Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate, having a component side and a system side; mounting a first integrated circuit die on the component side of the package substrate; mounting a second integrated circuit die on the component side of the package substrate; mounting an internal package, having an internal die, over the first integrated circuit die; coupling chip interconnects between the first integrated circuit die, the second integrated circuit die, the internal die, the component side, or a combination thereof, and forming a stacked package body by encapsulating the component side, the first integrated circuit die, the second integrated circuit die, the internal package, and the chip interconnects.Type: GrantFiled: March 13, 2009Date of Patent: August 26, 2014Assignee: STATS ChipPAC Ltd.Inventors: Hyunil Bae, YoungChul Kim, Myung Kil Lee
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Patent number: 8481371Abstract: A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant.Type: GrantFiled: May 20, 2011Date of Patent: July 9, 2013Assignee: STATS Chippac Ltd.Inventors: Youngcheol Kim, Myung Kil Lee, Gwang Kim, Koo Hong Lee
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Patent number: 8089143Abstract: An integrated circuit package system is provided in which an interposer of predetermined thickness including a central cavity is formed. Additionally, one or more contacts are formed around the central cavity on the interposer. The interposer is employed for connecting first and second packages.Type: GrantFiled: September 16, 2005Date of Patent: January 3, 2012Assignee: Stats Chippac Ltd.Inventor: Myung Kil Lee
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Patent number: 8026582Abstract: An integrated circuit package system comprising: providing a substrate; forming a base assembled package over the substrate; forming a top package over the base assemble package; and applying a top package stacking material for stand-off or insulation to the base assembled package and the top package.Type: GrantFiled: February 4, 2008Date of Patent: September 27, 2011Assignee: Stats Chippac Ltd.Inventors: Myung Kil Lee, Jae Chang Kim, Byung Ok Kim, legal representative, Koo Hong Lee
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Publication number: 20110215456Abstract: A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant.Type: ApplicationFiled: May 20, 2011Publication date: September 8, 2011Inventors: Youngcheol Kim, Myung Kil Lee, Gwang Kim, Koo Hong Lee
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Patent number: 7947535Abstract: A thin package system with external terminals and a leadframe is provided. An external bond finger defining template is provided and used to form external bond fingers on the leadframe. A die is provided and attached to the leadframe. At least portions of the die and the external bond fingers are encapsulated, and the leadframe is removed.Type: GrantFiled: October 22, 2005Date of Patent: May 24, 2011Assignee: STATS ChipPAC Ltd.Inventors: Youngcheol Kim, Myung Kil Lee, Gwang Kim, Koo Hong Lee
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Patent number: 7674640Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.Type: GrantFiled: August 24, 2007Date of Patent: March 9, 2010Assignee: STATS ChipPAC Ltd.Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung
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Publication number: 20090236723Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate, having a component side and a system side; mounting a first integrated circuit die on the component side of the package substrate; mounting a second integrated circuit die on the component side of the package substrate; mounting an internal package, having an internal die, over the first integrated circuit die; coupling chip interconnects between the first integrated circuit die, the second integrated circuit die, the internal die, the component side, or a combination thereof, and forming a stacked package body by encapsulating the component side, the first integrated circuit die, the second integrated circuit die, the internal package, and the chip interconnects.Type: ApplicationFiled: March 13, 2009Publication date: September 24, 2009Inventors: Hyunil Bae, YoungChul Kim, Myung Kil Lee
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Publication number: 20090194867Abstract: An integrated circuit package system comprising: providing a substrate; forming a base assembled package over the substrate; forming a top package over the base assemble package; and applying a top package stacking material for stand-off or insulation to the base assembled package and the top package.Type: ApplicationFiled: February 4, 2008Publication date: August 6, 2009Inventors: Myung Kil Lee, Jae Chang Kim, Byung Ok Kim, Koo Hong Lee
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Publication number: 20070268660Abstract: A spacerless semiconductor package chip stacking system is provided having a substrate. The substrate has at least one window therethrough. A first semiconductor device is attached face down on the top of the substrate. A second semiconductor device is attached face up on the back of the first semiconductor device. The first semiconductor device is electrically connected through the window to the bottom of the substrate. The second semiconductor device is electrically connected to the substrate.Type: ApplicationFiled: May 17, 2006Publication date: November 22, 2007Applicant: STATS CHIPPAC LTD.Inventors: Seungyun Ahn, Youngcheol Kim, Haengcheol Choi, Myung Kil Lee, JoHyun Bae, Hyunil Bae, Junwoo Myung
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Patent number: 7279785Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.Type: GrantFiled: November 12, 2005Date of Patent: October 9, 2007Assignee: Stats Chippac Ltd.Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung
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Publication number: 20070109750Abstract: An integrated circuit package system is provided forming a substrate having an integrated circuit die attached thereon, attaching a heat slug on the substrate, the heat slug having a planar top surface and an opening in the planar top surface, and molding the heat slug and the substrate through the opening.Type: ApplicationFiled: April 27, 2006Publication date: May 17, 2007Applicant: STATS ChipPAC Ltd.Inventors: Myung Kil Lee, Flynn Carson
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Publication number: 20070090495Abstract: A thin package system with external terminals and a leadframe is provided. An external bond finger defining template is provided and used to form external bond fingers on the leadframe. A die is provided and attached to the leadframe. At least portions of the die and the external bond fingers are encapsulated, and the leadframe is removed.Type: ApplicationFiled: October 22, 2005Publication date: April 26, 2007Applicant: STATS CHIPPAC LTD.Inventors: Youngcheol Kim, Myung Kil Lee, Gwang Kim, Koo Hong Lee
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Publication number: 20060180914Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.Type: ApplicationFiled: November 12, 2005Publication date: August 17, 2006Applicant: STATS CHIPPAC LTD.Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung
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Publication number: 20060175695Abstract: An integrated circuit package system is provided in which an interposer of predetermined thickness is formed. A central portion of the interposer is removed, thereby forming a cavity. Additionally, one or more contacts are formed around the central cavity on the interposer. The interposer is employed for connecting first and second packages.Type: ApplicationFiled: September 16, 2005Publication date: August 10, 2006Applicant: STATS CHIPPAC LTD.Inventor: Myung Kil Lee