Abstract: A pharmaceutical composition containing multi-target protein kinase inhibitor compounds, and the use thereof. The pharmaceutical composition contains compounds shown in formula II and formula A or formula B as active ingredients, and an excipient. The pharmaceutical composition has the characteristics of a simple preparation method, a smooth preparation process and suitability for industrial production. Moreover, an oral preparation prepared from the pharmaceutical composition, especially an oral solid preparation, has advantageous preparation properties such as dissolution rate and content uniformity, and excellent stability; and same is suitable for use and storage as a medicine.

Abstract: A method of training a neural network to approximate a forecasting error of a passenger-demand forecasting model that includes calculating, using the forecasting model, a historical passenger demand forecast for each key level in a set of key levels and for each departure date in a set of historical departures dates; applying a dropout model to the historical passenger demand forecasts to create a training sample; training, using the historical passenger demand forecasts and the training sample, the neural network, to approximate forecasting errors associated with the forecasting model; calculating, using the forecasting model, a future passenger demand forecast for each key level in the set of key levels and for each departure date in a set of future dates; and approximating, using the trained neural network, the forecasting error associated with the future passenger demand forecasts for the second set of departure dates.

Abstract: A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals.

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals.

Abstract: The present invention discloses a circuit for improving process robustness of sub-threshold SRAM memory cells, which serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to the PMOS tube of the sub-threshold SRAM memory cell and the substrate of a PMOS tube in the circuit. The circuit comprises a detection circuit for threshold voltage of PMOS tube and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS tubes in the sub-threshold SRAM memory cell and the substrate voltage of the PMOS tube in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS tubes and NMOS tubes resulted from process fluctuations and thereby regulate the threshold voltages of the PMOS tubes, so that the threshold voltage of PMOS tubes matches the threshold voltage of NMOS tubes.

Abstract: The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.

Abstract: The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.

Abstract: A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1˜N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the NMOS transistors N1 and N2, are grounded respectively; the NMOS transistor N1 form an phase inverter with the PMOS transistor P1, and the NMOS transistor N2 form another phase inverter with the PMOS transistor P2; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N5, the output end of the phase inverter N1 and P1 directly connected to the input end of the phase inverter N2 and P2, and the output end of the phase inverter N2 and P2 connected to the input end of the phase inverter N1 and P1 via the cut-off NMOS transistor N5; the NMOS transistor N3 is connected with the write bit line (WBL) of the phase inverter N1 and P1, and the NMO

Abstract: A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.

Abstract: A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.

Abstract: A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1˜N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the NMOS transistors N1 and N2, are grounded respectively; the NMOS transistor N1 form an phase inverter with the PMOS transistor P1, and the NMOS transistor N2 form another phase inverter with the PMOS transistor P2; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N5, the output end of the phase inverter N1 and P1 directly connected to the input end of the phase inverter N2 and P2, and the output end of the phase inverter N2 and P2 connected to the input end of the phase inverter N1 and P1 via the cut-off NMOS transistor N5; the NMOS transistor N3 is connected with the write bit line (WBL) of the phase inverter N1 and P1, and the NMO