Abstract: Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.

Abstract: Embodiments of methods and apparatuses for multicast handling in mixed core systems have been described. A method for multicast handling in mixed core systems includes configuring broadcast group registers located in targets. The method also includes receiving a request to create a broadcast group and creating the broadcast group. Finally, the method includes transmitting the broadcast group to targets with broadcast group registers that correspond to the broadcast group.

Abstract: A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.

Abstract: A communication system and method with configurable posting points have been described.

Abstract: A content addressable memory (CAM) device (300) can receive a compare data value having a native word size. The compare data value can be split into smaller portions, with one portion can be applied to a first CAM block (302-0) and another being applied to a second CAM block (302-1) on a subsequent clock (CAMCLK) cycle. Activation of circuit elements in the second CAM block (302-1) can be conditioned on first match results (CMATCHA0 to CMATCHAn) generated by first CAM block (302-0).

Abstract: A method and apparatus for multicast handling in mixed core systems have been described.

Abstract: A communication system and method with configurable posting points have been described.

Abstract: A method and apparatus for composing on-chip interconnects with configurable interfaces have been described.

Abstract: A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.

Abstract: An algorithm for selecting a directory entry in a multiprocessor-node system. In response to a memory request from a processor in a processor node, the algorithm finds an available entry to store information about the requested memory line. If at least one entry is available, then the algorithm uses one of the available entries. Otherwise, the algorithm searches for a “shared” entry. If at least one shared entry is available, then the algorithm uses one of the shared entries. Otherwise, the algorithm searches for a “dirty” entry. If at least one dirty entry is available, then the algorithm uses one of the dirty entries. In selecting a directory entry, the algorithm uses a “least-recently-used” (LRU) algorithm because an entry that was not recently used is more likely to be stale. Further, to improve system performance, the algorithm preferably uses a shared entry before using a dirty entry.

Abstract: An algorithm for selecting a directory entry in a multiprocessor-node system. In response to a memory request from a processor in a processor node, the algorithm finds an available entry to store information about the requested memory line. If at least one entry is available, then the algorithm uses one of the available entries. Otherwise, the algorithm searches for a “shared” entry. If at least one shared entry is available, then the algorithm uses one of the shared entries. Otherwise, the algorithm searches for a “dirty” entry. If at least one dirty entry is available, then the algorithm uses one of the dirty entries. In selecting a directory entry, the algorithm uses a “least-recently-used” (LRU) algorithm because an entry that was not recently used is more likely to be stale. Further, to improve system performance, the algorithm preferably uses a shared entry before using a dirty entry.