Patents by Inventor Nadeem Haq

Nadeem Haq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9932813
    Abstract: Calibrating Friction Factors. At least some of the illustrative embodiments are methods including: calibrating friction factor for a drilling operation by: plotting on a display device the expected hook load versus depth for the drilling operation; displaying plot points on the display device, each plot point indicative of a measured hook load versus depth for the drilling operation; selecting a plot point associated with a depth, the selecting responsive to a cursor hovering over the plot point on the display device; displaying a friction factor values which correlates the expected hook load versus depth for the particular depth to the measured hook load versus depth for the plot point, selecting the value responsive to the cursor hovering over the value; and then shifting on the display device at least a portion of the indication of expected hook load versus depth based on the value of friction factor.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 3, 2018
    Assignee: LANDMARK GRAPHICS CORPORATION
    Inventors: Nadeem A. Haq, Gustavo A. Urdaneta, Robello Samuel
  • Publication number: 20160092482
    Abstract: An illustrative scenario compiling method that includes providing a visual representation of a well having well components mapped to different areas of the visual representation, responding to a selection of one of the well components with a list of data sets corresponding to the well component, retrieving a selected data set from a corresponding database, storing the data set in a common location with selected data sets of other well components, and saving the selected data sets as a scenario to be used for assembling a future collection of data sets as input for analysis software.
    Type: Application
    Filed: May 13, 2014
    Publication date: March 31, 2016
    Applicant: LANDMARK GRAPHICS CORPORATION
    Inventors: Nadeem A. Haq, Gustavo Adolfo Urdaneta
  • Publication number: 20150361779
    Abstract: Calibrating Friction Factors. At least some of the illustrative embodiments are methods including: calibrating friction factor for a drilling operation by: plotting on a display device the expected hook load versus depth for the drilling operation; displaying plot points on the display device, each plot point indicative of a measured hook load versus depth for the drilling operation; selecting a plot point associated with a depth, the selecting responsive to a cursor hovering over the plot point on the display device; displaying a friction factor values which correlates the expected hook load versus depth for the particular depth to the measured hook load versus depth for the plot point, selecting the value responsive to the cursor hovering over the value; and then shifting on the display device at least a portion of the indication of expected hook load versus depth based on the value of friction factor.
    Type: Application
    Filed: February 27, 2013
    Publication date: December 17, 2015
    Applicant: LANDMARK GRAPHICS CORPORATION
    Inventors: Nadeem A. Haq, Gustavo A. Urdaneta, Robello Samuel
  • Patent number: 6449274
    Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: September 10, 2002
    Assignee: PMC-Sierra, Inc.
    Inventors: Brian D. Holden, Brian D. Alleyne, Darren S. Braun, Imran Chaudhri, Kevin Reno, Nadeem Haq, Chee Hu, Raghavan P Menon, Steve T Sprouse, Dinesh Venkatachalam
  • Patent number: 6445705
    Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: September 3, 2002
    Assignee: PMC-Sierra, Inc.
    Inventors: Brian D. Holden, Brian D. Alleyne, Darren S. Braun, Nadeem Haq, Chee Hu
  • Patent number: 6396809
    Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: May 28, 2002
    Assignee: PMC-Sierra, Inc.
    Inventors: Brian D. Holden, Brian D. Alleyne, Darren S. Braun, Nadeem Haq
  • Patent number: 5857007
    Abstract: In a CT imaging system which includes a gantry having a rotatable ring member and a DAS comprising circuit boards grouped in a selected number of sets, a DAS housing is provided which is disposed to dissipate heat away from the DAS circuit boards. The housing includes a frame for mounting each of the circuit boards on the gantry ring so that the boards of a set are in spaced-apart relationship with each other, and further includes a cover for each frame, to form an enclosure for the circuit boards supported thereby. Each cover is provided with a panel member, a section of each panel being provided with a specified pattern of perforations. Each panel is positioned with respect to its set of circuit boards to provide an unobstructed space of selected dimension between its pattern of perforations and its corresponding circuit board set.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: January 5, 1999
    Assignee: General Electric Company
    Inventor: Nadeem Haq