Abstract: There is disclosed an array (10) of split-gate non-volatile memory cells (24) supplied with power at a low voltage (VDD) by a power supply (30), said cells being arranged in one or more rows and columns and electrically interconnected in groups to form one or more pages (12). The array comprises control logic (32) delivering a defined programming voltage (VPROG) that is close or or substantially equal to the low power supply voltage that is applied to a control gate (245) of at least one cell (24A) that is to be programmed via a word control line (18) corresponding to that cell and blocking logic (36) delivering a first blocking voltage (VBLOC1) that is greater than said low power supply voltage and is applied to the first regions (241) of the cells (24B) sharing the same word control line (18) as said cell that is to be programmed via a bit control line (22) corresponding to those cells.