Patents by Inventor Nae Hisano
Nae Hisano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230383749Abstract: A liquid-cooled rotary compressor includes a compressor main body having a compression chamber formed by a fixed wall and a rotating wall and compressing gas, and a liquid injection path for injecting a coolant into the compression chamber, and adjusts a discharge flow rate by changing a rotational speed of the rotating wall. The compressor includes a liquid amount adjusting unit that adjusts an amount of the coolant supplied from the liquid injection path to the compressor main body according to a change in the rotational speed of the rotating wall, and a compressed gas supply path that supplies compressed gas to a downstream side of the liquid amount adjusting unit in the liquid injection path. The compressed gas is supplied from the compressed gas supply path to the liquid injection path according to the amount of the coolant supplied to the compressor main body.Type: ApplicationFiled: March 15, 2023Publication date: November 30, 2023Inventors: Nae HISANO, Ryota IIJIMA, Kotaro CHIBA, Takeshi TSUCHIYA
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Publication number: 20230366400Abstract: A gas compressor includes a compression mechanism, a separator tank that introduces lubricating oil to be supplied to the compression mechanism and a mixed fluid of a working fluid and the lubricating oil discharged from the compression mechanism and separates the lubricating oil, an oil cooler that cools the lubricating oil from the separator tank, an oil circulation path that supplies the cooled lubricating oil to the compression mechanism, and a motor that drives the compression mechanism and is isolated from the oil circulation path.Type: ApplicationFiled: March 17, 2023Publication date: November 16, 2023Inventors: Ryota IIJIMA, Kotaro CHIBA, Nae HISANO
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Patent number: 10522799Abstract: A battery pack that reduces a temperature difference between single cells and can increase a battery capacity per volume and a container provided with the same are provided. A battery pack 100, includes: a battery module 10 including a plurality of single cells 1 arranged in parallel in a line; and a partition member 20 provided on a side surface of the battery module 10 and forming a flow channel 21 through which a gas for exchanging heat with the plurality of single cells 1 is flowable, and the partition member 20 is provided so that the gas flowing through the flow channel 21 and at least two single cells 1 exchange heat and is inclined with respect to a direction orthogonal to an arrangement direction of the plurality of single cells 1 arranged in parallel in a line.Type: GrantFiled: July 31, 2013Date of Patent: December 31, 2019Assignee: HITACHI, LTD.Inventors: Nae Hisano, Shin Yamauchi, Mitsutoshi Honda, Hidekazu Fujimura, Kenji Takeda
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Publication number: 20150214521Abstract: A battery pack that reduces a temperature difference between single cells and can increase a battery capacity per volume and a container provided with the same are provided. A battery pack 100, includes: a battery module 10 including a plurality of single cells 1 arranged in parallel in a line; and a partition member 20 provided on a side surface of the battery module 10 and forming a flow channel 21 through which a gas for exchanging heat with the plurality of single cells 1 is flowable, and the partition member 20 is provided so that the gas flowing through the flow channel 21 and at least two single cells 1 exchange heat and is inclined with respect to a direction orthogonal to an arrangement direction of the plurality of single cells 1 arranged in parallel in a line.Type: ApplicationFiled: July 31, 2013Publication date: July 30, 2015Applicant: Hitachi, Ltd.Inventors: Nae Hisano, Shin Yamauchi, Mitsutoshi Honda, Hidekazu Fujimura, Kenji Takeda
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Patent number: 8937390Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: GrantFiled: March 6, 2014Date of Patent: January 20, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
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Publication number: 20140183730Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
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Patent number: 8704352Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: GrantFiled: January 6, 2010Date of Patent: April 22, 2014Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
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Patent number: 8334465Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.Type: GrantFiled: September 30, 2008Date of Patent: December 18, 2012Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
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Publication number: 20100171213Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: ApplicationFiled: January 6, 2010Publication date: July 8, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
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Patent number: 7618847Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.Type: GrantFiled: August 7, 2008Date of Patent: November 17, 2009Assignees: Elpida Memory, Inc., Hitachi, Ltd.Inventors: Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano, Hiroaki Ikeda, Masakazu Ishino
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Patent number: 7573128Abstract: A semiconductor module comprises: semiconductor packages each comprising a semiconductor element, a wiring substrate having a wiring member connected to the semiconductor element and external terminals connected to the wiring member, and a first organic film formed on a side of the semiconductor element opposed to a side toward the wiring substrate; and a mount substrate, on which the semiconductor element is mounted. First of the semiconductor packages and second of the semiconductor packages are stacked. Second organic films are provided between the wiring substrate of the first semiconductor package and the first organic film of the second semiconductor package and between the mount substrate and the semiconductor package.Type: GrantFiled: April 29, 2004Date of Patent: August 11, 2009Assignee: Hitachi, Ltd.Inventors: Hisashi Tanie, Nae Hisano, Koji Hosokawa
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Publication number: 20090134498Abstract: The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material.Type: ApplicationFiled: November 19, 2008Publication date: May 28, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Hiroaki IKEDA, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama, Yasuhiro Naka, Nae Hisano, Hisashi Tanie, Kunihiko Nishi, Hiroyuki Tenmei
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Publication number: 20090109641Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.Type: ApplicationFiled: September 30, 2008Publication date: April 30, 2009Applicant: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
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Publication number: 20090072414Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.Type: ApplicationFiled: August 7, 2008Publication date: March 19, 2009Inventors: Hiroyuki TENMEI, Kunihiko NISHI, Yasuhiro NAKA, Nae HISANO, Hiroaki IKEDA, Masakazu ISHINO
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Patent number: 7477520Abstract: In a memory module, a plurality of semiconductor memory packages are arranged and mounted on a module board, and a control semiconductor package is disposed in a central region of the arrangement of the semiconductor memory packages, and mounted on the module board. A control semiconductor radiator thermally connected to the control semiconductor package, and a semiconductor memory radiator thermally connected to the plurality of memory packages are disposed without being thermally connected to each other in relation to a direction in which the semiconductor memory packages are arranged.Type: GrantFiled: March 29, 2006Date of Patent: January 13, 2009Assignee: Elpida Memory, Inc.Inventors: Masanori Shibamoto, Nae Hisano
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Patent number: 7432594Abstract: A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first and second electrically conductive members covering the first and second electrode surfaces respectively as seen in the thickness direction to be electrically connected to the first and second electrode surfaces respectively.Type: GrantFiled: June 30, 2005Date of Patent: October 7, 2008Assignee: Renesas Technology Corp.Inventors: Kisho Ashida, Akira Muto, Ichio Shimizu, Toshiyuki Hata, Kenya Kawano, Naotaka Tanaka, Nae Hisano
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Publication number: 20060244126Abstract: In a memory module, a plurality of semiconductor memory packages are arranged and mounted on a module board, and a control semiconductor package is disposed in a central region of the arrangement of the semiconductor memory packages, and mounted on the module board. A control semiconductor radiator thermally connected to the control semiconductor package, and a semiconductor memory radiator thermally connected to the plurality of memory packages are disposed without being thermally connected to each other in relation to a direction in which the semiconductor memory packages are arranged.Type: ApplicationFiled: March 29, 2006Publication date: November 2, 2006Inventors: Masanori Shibamoto, Nae Hisano
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Patent number: 7119428Abstract: A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.Type: GrantFiled: December 28, 2004Date of Patent: October 10, 2006Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Hisashi Tanie, Nae Hisano, Hiroyuki Ohta, Hiroaki Ikeda, Ichiro Anjo, Mitsuaki Katagiri, Yuji Watanabe
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Publication number: 20060043618Abstract: A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first and second electrically conductive members covering the first and second electrode surfaces respectively as seen in the thickness direction to be electrically connected to the first and second electrode surfaces respectively.Type: ApplicationFiled: June 30, 2005Publication date: March 2, 2006Applicant: Renesas Technology Corp.Inventors: Kisho Ashida, Akira Muto, Ichio Shimizu, Toshiyuki Hata, Kenya Kawano, Naotaka Tanaka, Nae Hisano
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Publication number: 20050189639Abstract: A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.Type: ApplicationFiled: December 28, 2004Publication date: September 1, 2005Applicants: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Hisashi Tanie, Nae Hisano, Hiroyuki Ohta, Hiroaki Ikeda, Ichiro Anjoh, Mitsuaki Katagiri, Yuji Watanabe