Patents by Inventor Naeem Ibrahim Ally

Naeem Ibrahim Ally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942953
    Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: March 26, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Kaushik Mazumdar, Joyce Cheuk Wai Wong, Naeem Ibrahim Ally, Stephen Victor Kosonocky
  • Publication number: 20230198528
    Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Kaushik Mazumdar, Joyce Cheuk Wai Wong, Naeem Ibrahim Ally, Stephen Victor Kosonocky
  • Patent number: 11108382
    Abstract: An oscillator circuit includes a first oscillator, a second oscillator, and a calibration circuit to calibrate the first and second oscillators. The first oscillator is supplied with a first supply voltage, and the second oscillator is supplied with a second supply voltage. The calibration includes setting a frequency control of the second oscillator at a target frequency. Then, a voltage control of the second supply voltage is adjusted incrementally until a first control value is identified at which a second oscillator output frequency matches the target frequency. Then, a voltage control of the first supply voltage is set to the first control value. Then, the voltage control for the first supply voltage is adjusted incrementally until a second control value is identified at which a first oscillator output frequency is as close to the second oscillator output frequency as is achievable, but does not exceed it.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 31, 2021
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Joyce Cheuk Wai Wong, Naeem Ibrahim Ally, Jonathan Hauke, Stephen Victor Kosonocky