Patents by Inventor Nagaraj N. Savithri
Nagaraj N. Savithri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8112737Abstract: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.Type: GrantFiled: September 19, 2008Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Nagaraj N. Savithri, Dharin Nayeshbhai Shah, Girishankar Gurumurthy
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Publication number: 20090013297Abstract: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.Type: ApplicationFiled: September 19, 2008Publication date: January 8, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Nagaraj N. Savithri, Dharin Nayeshbhai Shah, Girishankar Gurumurthy
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Patent number: 7441218Abstract: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.Type: GrantFiled: May 24, 2006Date of Patent: October 21, 2008Assignee: Texas Instruments IncorporatedInventors: Nagaraj N. Savithri, Dharin Nayeshbhai Shah, Girishankar Gurumurthy
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Publication number: 20070277137Abstract: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.Type: ApplicationFiled: May 24, 2006Publication date: November 29, 2007Inventors: Nagaraj N. Savithri, Dharin Nayeshbhai Shah, Girishankar Gurumurthy
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Patent number: 6732339Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.Type: GrantFiled: November 20, 2002Date of Patent: May 4, 2004Assignee: Texas Instruments IncorporatedInventors: Nagaraj N. Savithri, John Apostol, Anthony M.-Hill
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Publication number: 20030079191Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.Type: ApplicationFiled: November 20, 2002Publication date: April 24, 2003Inventors: Nagaraj N. Savithri, John Apostol, Anthony M. Hill
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Patent number: 6499131Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups.Type: GrantFiled: June 30, 2000Date of Patent: December 24, 2002Assignee: Texas Instruments IncorporatedInventors: Nagaraj N. Savithri, Franciso A. Cano
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Patent number: 6493853Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.Type: GrantFiled: July 17, 2000Date of Patent: December 10, 2002Assignee: Texas Instruments IncorporatedInventors: Nagaraj N. Savithri, John Apostol, Anthony M. Hill
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Patent number: 6378109Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures of transistor gate oxide. A methodology is provided that is a practical approach to full-chip crosstalk noise verification and gate oxide integrity analysis. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups. Selected signal lines are then fully simulated to determine gate oxide field strengths on transistors connected to the selected signal lines.Type: GrantFiled: June 30, 2000Date of Patent: April 23, 2002Assignee: Texas Instruments IncorporatedInventors: Duane J. Young, Franciso A. Cano, Nagaraj N. Savithri
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Patent number: 6363516Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A method is provided for extracting parasitic data in a hierarchical manner from a trial layout of the integrated circuit. Intracellular parasitic data representative each cell type used in the integrated circuit is extracted only once, regardless of the number of times the cell is instantiated in the integrated circuit. For each instance of each cell, a portion of intercell signal lines that are routed over that instance of the cell are cut out in cookie cutter fashion by specifying an area in the trial layout corresponding to the instance of the cell such that the portion of intercell signal lines within the area can be processed apart from the remaining portion of the intercell signal lines.Type: GrantFiled: November 12, 1999Date of Patent: March 26, 2002Assignee: Texas Instruments IncorporatedInventors: Francisco A. Cano, Nagaraj N. Savithri, Vijaya Gunturi
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Patent number: 6253359Abstract: A method for designing and fabricating an integrated circuit is described. An increase or a decrease in a total propagation delay time 311 of a signal on a victim net 203 is accurately modeled using a modified decoupled simulation model 300. Victim net 203 is modeled as a distributed capacitor 320a-c that has a total value equal to Cgnd+2*K*Ccoup. A match propagation delay time which includes a variation in propagation delay caused by signal coupling from aggressor nets located adjacent to the victim net is determined by simulating a representative circuit using a coupled distributed load simulation model to accurately determine the match propagation delay time. K is determined using an equation in which K=1+(match delay−unmodified delay)/(2*R*Ccoup). R is the effective drive resistance of a buffer which drives the victim net and associated signal trace resistance.Type: GrantFiled: January 29, 1999Date of Patent: June 26, 2001Assignee: Texas Instruments IncorporatedInventors: Francisco A. Cano, Nagaraj N. Savithri, Deepak Kapoor
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Patent number: 6038383Abstract: A method for designing and fabricating an integrated circuit is disclosed. Signal line interconnect widths are determined by performing an electromigration analysis on a trial layout of the integrated circuit. A representative circuit for an integrated circuit is designed and a trial layout is created that includes a plurality of nets. A preprocessor 505 eliminates nets that do not need further validation. An extraction process 510 generates an RC network representation of each remaining net that is to be validated to form a distributed load simulation model. Distributed capacitance and resistance of signal lines is included with load capacitance of receivers to provide an accurate profile of current flow. A profile of current flowing in the signal line of each net is determined by simulating the operation of each net using simulator 517. Peak current, RMS current and average current is determined.Type: GrantFiled: October 13, 1997Date of Patent: March 14, 2000Assignee: Texas Instruments IncorporatedInventors: Duane J. Young, Francisco A. Cano, Nagaraj N Savithri, Haldun Haznedar