Patents by Inventor Nagaraja Reddy Anakala
Nagaraja Reddy Anakala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11032769Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.Type: GrantFiled: December 18, 2017Date of Patent: June 8, 2021Assignee: Silicon Laboratories Inc.Inventors: Partha Sarathy Murali, Nagaraja Reddy Anakala, Ajay Mantha
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Patent number: 10620661Abstract: A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.Type: GrantFiled: December 17, 2018Date of Patent: April 14, 2020Assignee: Redpine Signals, Inc.Inventors: Partha Sarathy Murali, Nagaraja Reddy Anakala
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Publication number: 20190191372Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Applicant: Redpine Signals, Inc.Inventors: Partha Sarathy Murali, Nagaraja Reddy Anakala, Ajay Mantha
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Publication number: 20190187745Abstract: A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.Type: ApplicationFiled: December 17, 2018Publication date: June 20, 2019Applicant: Redpine Signals, Inc.Inventors: Partha Sarathy MURALI, Nagaraja Reddy ANAKALA
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Publication number: 20190149343Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.Type: ApplicationFiled: November 14, 2017Publication date: May 16, 2019Applicant: Redpine Signals, Inc.Inventors: Partha Sarathy Murali, Ajay MANTHA, Nagaraja Reddy ANAKALA, Subba Reddy KALLAM, Venkat MATTELA
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Patent number: 8149965Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.Type: GrantFiled: September 16, 2008Date of Patent: April 3, 2012Assignee: Redpine Signals, Inc.Inventors: Dharani Naga Sailaja Sankabathula, Partha Sarathy Murali, Logeshwaran Vijayan, Nagaraja Reddy Anakala
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Patent number: 8149966Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.Type: GrantFiled: September 16, 2008Date of Patent: April 3, 2012Assignee: Redpine Signals, Inc.Inventors: Dharani Naga Sailaja Sankabathula, Partha Sarathy Murali, Logeshwaran Vijayan, Nagaraja Reddy Anakala
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Patent number: 8090062Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.Type: GrantFiled: September 16, 2008Date of Patent: January 3, 2012Assignee: Redpine Signals, Inc.Inventors: Dharani Naga Sailaja Sankabathula, Partha Sarathy Murali, Logeshwaran Vijayan, Nagaraja Reddy Anakala
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Patent number: 8090035Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.Type: GrantFiled: September 16, 2008Date of Patent: January 3, 2012Assignee: Redpine Signals, Inc.Inventors: Dharani Naga Sailaja Sankabathula, Partha Sarathy Murali, Logeshwaran Vijayan, Nagaraja Reddy Anakala
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Publication number: 20100067626Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Inventors: Salaja Dharani Naga SANKABATHULA, Partha Sarathy Murali, Logeshwaran Vijayan, Nagaraja Reddy Anakala
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Publication number: 20100067625Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Inventors: Dharani Naga Sailaja SANKABATHULA, Partha Sarathy Murali, Logeshwaran Vijayan, Nagaraja Reddy Anakala
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Publication number: 20100067624Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Inventors: Salaja Dharani Naga SANKABATHULA, Partha Sarathy Murali, Logeshwaran Vijayan, Nagaraja Reddy Anakala
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Publication number: 20100067623Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Inventors: Dharani Naga Sailaja SANKABATHULA, Partha Sarathy Murali, Logeshwaran Vijayan, Nagaraja Reddy Anakala