Abstract: A system and method for providing timing and placement co-optimization for engineering change order (ECO) cells is described. According to one embodiment, an ECO for a current design of an integrated circuit is accessed. The ECO includes inserting an ECO cell among placed and routed current cells of the current design. A target region in the current design is identified for placement of the ECO cell, but the target region has insufficient open space to place the ECO cell. At least one current cell will have to be moved in order to place the ECO cell in the target region. Timing slacks for current cells in a neighborhood of the target region are determined. Based on the timing slacks of the current cells, at least one of the current cells is moved to a different location to create sufficient open space to place the ECO cell within the target region.

Abstract: A method and apparatus for preforming engineering change order scenario compression by applying a hybrid of live and static timing views to an integrated circuit design. A plurality of operational scenarios are identified with at least one operational condition. The operational status for a plurality of operational features is determined under conditions associated with the identified scenarios. The operational scenarios are divided into live and static views. Margins are then associated with the operational features within at least one scenario of a static view. Information is transferred from at least one scenario of a static view to a merged live view through the margin.

Abstract: A method of optimizing a power consumption of an integrated circuit design, includes dividing the integrated circuit design into N circuit partitions, supplying each circuit partition to a different one of N computer systems each associated with a different one of the N circuit partitions, training each of the N computer systems to reduce the power consumption of its associated circuit partition thereby to generate N training data, storing the N training data in a database, and applying the N training data to the integrated circuit design thereby to reduce the consumption of the integrated circuit design.

Abstract: An EDA tool trains a machine-learning optimization tool using quantized optimization solution (training) data generated by conventional optimization tools. Each training data entry includes an input vector and an associated output vector that have quantized component values respectively determined by associated operating characteristics of initial (non-optimal) and corresponding replacement (optimized) circuit portions, where each initial circuit portion is identified and replaced by the corresponding replacement circuit portion during optimization of an associated target IC design. The stored training data entries are used by the machine-learning optimization tool to generate an efficient (e.g., piecewise-linear) prediction function.

Abstract: An EDA tool trains a machine-learning optimization tool using quantized optimization solution (training) data generated by conventional optimization tools. Each training data entry includes an input vector and an associated output vector that have quantized component values respectively determined by associated operating characteristics of initial (non-optimal) and corresponding replacement (optimized) circuit portions, where each initial circuit portion is identified and replaced by the corresponding replacement circuit portion during optimization of an associated target IC design. The stored training data entries are used by the machine-learning optimization tool to generate an efficient (e.g., piecewise-linear) prediction function.

Abstract: Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.

Abstract: Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.

Abstract: A system and a method are disclosed for displaying an output of a static timing analysis. A plurality of timing violations of an integrated circuit is identified. The timing violations are associated with a timing path. A reason is identified for each of the timing violations. A priority for fixing the timing violations is determined. Information describing the timing violations is sent for being presented. The information presented includes an information indicating priority associated with timing violations to assist developers in prioritizing tasks for fixing the timing violations.

Abstract: A system and a method are disclosed for displaying an output of a static timing analysis. A plurality of timing violations of an integrated circuit is identified. The timing violations are associated with a timing path. A reason is identified for each of the timing violations. A priority for fixing the timing violations is determined. Information describing the timing violations is sent for being presented. The information presented includes an information indicating priority associated with timing violations to assist developers in prioritizing tasks for fixing the timing violations.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: Systems and techniques for fixing design requirement violations in a circuit design in multiple scenarios are described. During operation, a system can receive a scenario image and a multi-scenario ECO database. The scenario image can store parameter values for circuit objects in a scenario, and the multi-scenario ECO database can store a subset of parameter values for a subset of circuit objects in multiple scenarios. Next, the system can determine an engineering change order to fix one or more design requirement violations, which can involve estimating parameter values for circuit objects in multiple scenarios using parameter values stored in the scenario image and the multi-scenario ECO database.

Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of signal paths, the time-delay contribution from each of these crosstalk aggressors may be modeled as a corresponding statistical random variable. Because the number of crosstalk aggressors are usually much larger than the number of stages in the signal path, the calculated total path delay may be less pessimistic. Furthermore, in order to detect potential timing violations, the time-delay contributions from additional dominant crosstalk aggressors can be modeled using non-statistical worst-case deterministic values.

Abstract: Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation.

Abstract: A computer is programmed to identify a number of groups of timing windows, each group including a victim timing window and one (or more) aggressor timing window(s), respectively for a victim net and one (or more) aggressor nets in an IC design. The computer automatically slides (i.e. shifts in time) the victim and aggressor timing windows as a group for each die, i.e. by a specific amount that is identical for all timing windows of an instance of a coupled stage in a die, but differs for other instances of the same coupled stage in other dies. Crosstalk analysis is then performed, using time-shifted timing windows which result from sliding, to identify overlapping victim and aggressor nets, followed by variation aware delay calculations to identify timing violations and timing critical nets, followed by revision of the IC design, which is eventually fabricated in a wafer of semiconductor material.

Abstract: Systems and techniques for fixing design requirement violations in a circuit design in multiple scenarios are described. During operation, a system can receive a scenario image and a multi-scenario ECO database. The scenario image can store parameter values for circuit objects in a scenario, and the multi-scenario ECO database can store a subset of parameter values for a subset of circuit objects in multiple scenarios. Next, the system can determine an engineering change order to fix one or more design requirement violations, which can involve estimating parameter values for circuit objects in multiple scenarios using parameter values stored in the scenario image and the multi-scenario ECO database.

Abstract: Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation.

Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.