Abstract: According to one embodiment, a system is disclosed. The system includes one or more storage devices, a host bus adapter (HBA) and a bridging device coupled between the one or more storage device and the HBA. The bridging device includes a register having bits corresponding to each of the one or more storage devices. Each bit indicates whether staggered spin-up is enabled at a corresponding storage device.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.

Abstract: According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.

Abstract: A storage device is disclosed. The storage device includes a storage controller. The storage controller includes a direct memory access (DMA) Descriptor Manager (DM) to generate DMA descriptors by monitoring user data and a data integrity field (DIF) transferred between a host memory and a local memory based upon a function being performed.

Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.

Abstract: A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.

Abstract: According to one embodiment, a system is disclosed. The system includes an initiator device to transmit input/output (I/O) write data and a target device, coupled to the initiator device, to receive the write data from the initiator device as a first segment of data and a second segment of data. The target device re-transmits a transfer ready frame to force the initiator device to retransmit the second segment in response to detecting an uncorrectable error in the second segment.

Abstract: According to one embodiment, a system is disclosed. The system includes a central timeout manager (CTM) to receive timeout events from two or more clients and a search unit to search for a location in a list of timeout events to place a new received timeout event.

Abstract: According to one embodiment, a device is disclosed. The device includes a first protocol engine (PE) to process tasks to be forwarded to a first remote node, a remote node search unit (RNSU) having a three-dimensional (3-D) task list corresponding to tasks to be forwarded to the two or more sub-nodes, and a connection pointer to maintain a connection between the first PE and the first remote node.

Abstract: According to one embodiment, a system is disclosed. The system includes one or more storage devices, a host bus adapter (HBA) and a bridging device coupled between the one or more storage device and the HBA. The bridging device includes a register having bits corresponding to each of the one or more storage devices. Each bit indicates whether staggered spin-up is enabled at a corresponding storage device.

Abstract: Apparatus and systems, as well as methods and articles, may operate to relate a port multiplier (PM) tag associated with a frame information structure frame to a remote node context index and to a validity flag using a hardware PM look-up table in a host bus adapter.

Abstract: Apparatus and systems, as well as methods and articles, may bridge between a link layer and a transport layer in a multi-lane serial-attached small computer system interface (SCSI)-serial SCSI protocol (SAS-SSP) device. A lane number first-in first-out buffer (FIFO) array may operate to order frame processing such that frames associated with an input-output (IO) stream subset of a plurality of SAS-SSP frames received at a plurality of lane receive buffers are processed in an IO stream subset order.