Patents by Inventor Nai-Wei LIU
Nai-Wei LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9461018Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.Type: GrantFiled: April 17, 2015Date of Patent: October 4, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
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Patent number: 9379080Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.Type: GrantFiled: March 13, 2015Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
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Publication number: 20160118272Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.Type: ApplicationFiled: December 28, 2015Publication date: April 28, 2016Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
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Patent number: 9312148Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.Type: GrantFiled: March 16, 2015Date of Patent: April 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
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Publication number: 20160005702Abstract: An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Patent number: 9230902Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.Type: GrantFiled: July 31, 2014Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
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Publication number: 20150187605Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.Type: ApplicationFiled: March 16, 2015Publication date: July 2, 2015Inventors: Jing-Cheng LIN, Jui-Pin HUNG, Nai-Wei LIU, Yi-Chao MAO, Wan-Ting SHIH, Tsan-Hua TUNG
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Publication number: 20150187724Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.Type: ApplicationFiled: March 13, 2015Publication date: July 2, 2015Inventors: Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
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Patent number: 9064879Abstract: Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.Type: GrantFiled: September 8, 2011Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Pin Hung, Jing-Cheng Lin, Nai-Wei Liu, Chin-Chuan Chang, Chen-Hua Yu, Shin-Puu Jeng, Chin-Fu Kao, Yi-Chao Mao, Szu Wei Lu
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Publication number: 20150108634Abstract: A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on the pad, a polymer disposed over the die and patterned to provide a path for the conductive trace passing through, and a molding surrounding the die and the polymer. A top surface of the molding is substantially in a same level as a top surface of the polymer.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: NAI-WEI LIU, JUI-PIN HUNG, JING-CHENG LIN
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Patent number: 9000584Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.Type: GrantFiled: December 28, 2011Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
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Patent number: 8994171Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.Type: GrantFiled: March 12, 2013Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
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Patent number: 8975749Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.Type: GrantFiled: January 10, 2014Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
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Publication number: 20140339696Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
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Publication number: 20140264828Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Hua Chang, Cheng-Lin Huang, Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin
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Patent number: 8829676Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.Type: GrantFiled: June 28, 2011Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
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Publication number: 20140210080Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.Type: ApplicationFiled: January 29, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
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Publication number: 20140127898Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nai-Wei LIU, Zhen-Cheng WU, Cheng-Lin HUANG, Po-Hsiang HUANG, Yung-Chih WANG, Shu-Hui SU, Dian-HAU CHEN, Yuh-Jier MII
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Patent number: 8653664Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.Type: GrantFiled: July 8, 2010Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
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Publication number: 20130168848Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Cheng LIN, Jui-Pin HUNG, Nai-Wei LIU, Yi-Chao MAO, Wan-Ting SHIH, Tsan-Hua TUNG