Abstract: Two embodiments of an integrated circuit debug apparatus are described. In one embodiment, a test head is provided which houses channel cards configured with switches. The switches selectively connect channels of the channel card to a device signal panel attached to the test head. Connection pins on the device signal panel may be coupled to various debug devices to allow debug of the device under test. The conductors which connect the device signal panel to the switch may be short compared to conductors which connect the test head to the integrated circuit tester. Therefore, debugging may be performed with the tests executing at higher clock rates than clock rates generated by debug equipment within the integrated circuit tester. A second embodiment is described in which ribbon cable connectors are added to the probe card used in the prober. Ribbon cables are coupled between the ribbon cable connectors and a device signal panel.