Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.

Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.

Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.

Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.

Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.

Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.

Abstract: Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.

Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

Abstract: An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.

Abstract: An encoding apparatus in accordance with an embodiment of the present invention includes: an encoder configured to request for storage of an original frame; a frame processing unit configured to generate an encoded frame having the original framed encoded therein; and a frame memory configured to store the encoded frame. Here, the frame processing unit is configured to generate the original frame by encoding the encoded frame stored in the frame memory according to a request of the encoder, and the encoder is configured to perform encoding according to the original frame.

Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.

Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.

Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.

Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

Abstract: Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.

Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.

Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.

Abstract: An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.

Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.

Abstract: Disclosed herein are motion estimation apparatus and method. The motion estimation apparatus may determine an SAD of a coding unit in a current image and calculate an average SAD of the current image. The motion estimation apparatus may compare the SAD of the coding unit with the average SAD of the current image, and determine the number of one or more previous images to be used for motion estimation of the coding unit based on the results of comparison.