Abstract: A semiconductor device includes a substrate provided with a decoupling capacitor and plurality of circuit elements disposed along a first direction, and a plurality of first wiring line patterns disposed in a first wiring line layer over the substrate, including a power routing pattern coupled to the decoupling capacitor and a plurality of internal wiring line patterns coupled to the plurality of circuit elements. The plurality of first wiring line patterns extend in the first direction, and are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting the first direction and parallel to the substrate.

Abstract: A semiconductor device includes a substrate provided with a decoupling capacitor and plurality of circuit elements disposed along a first direction, and a plurality of first wiring line patterns disposed in a first wiring line layer over the substrate, including a power routing pattern coupled to the decoupling capacitor and a plurality of internal wiring line patterns coupled to the plurality of circuit elements. The plurality of first wiring line patterns extend in the first direction, and are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting the first direction and parallel to the substrate.

Abstract: A semiconductor device that includes active patterns defined in a substrate, and gate patterns extending in a first direction while traversing the active patterns. First wiring line patterns disposed over a first dielectric layer which covers the gate patterns, and extending in the first direction. The first wiring line patterns comprise internal wiring line patterns coupled with first vertical vias, which pass through the first dielectric layer and are coupled to the active patterns and the gate patterns, and power routing patterns not coupled with the first vertical vias. The first wiring line patterns are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting with the first direction, and the first active patterns are disposed between the power routing patterns when viewed on a top.

Abstract: A semiconductor device that includes active patterns defined in a substrate, and gate patterns extending in a first direction while traversing the active patterns. First wiring line patterns disposed over a first dielectric layer which covers the gate patterns, and extending in the first direction. The first wiring line patterns comprise internal wiring line patterns coupled with first vertical vias, which pass through the first dielectric layer and are coupled to the active patterns and the gate patterns, and power routing patterns not coupled with the first vertical vias. The first wiring line patterns are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting with the first direction, and the first active patterns are disposed between the power routing patterns when viewed on a top.

Abstract: A semiconductor memory device includes a peripheral circuit including first and second circuit blocks that are respectively disposed in second and third regions adjacent to each other in a first direction with a first region interposed therebetween, first power lines disposed in a first metal layer and connected to the first unit circuit block, second power lines disposed in the first metal layer and connected to the second unit circuit block, and bridge power lines disposed in a second metal layer in the first region and extending in a second direction intersecting with the first direction. The first power lines extend from the second region to the first region and are meshed with the bridge power lines. The second power lines extend from the third region to the first region and are meshed the bridge power lines.

Abstract: A semiconductor memory device includes a peripheral circuit including a first unit circuit block and a second unit circuit block that are respectively disposed in a second region and a third region adjacent to each other in a first direction with a first region interposed therebetween, a first metal layer disposed over the peripheral circuit, a second metal layer disposed over the first metal layer, first power lines disposed in the first metal layer and suitable for transferring operating voltages to the first unit circuit block, second power lines disposed in the first metal layer and suitable for transferring the operating voltages to the second unit circuit block, and bridge power lines disposed in the second metal layer in the first region, and extending in a second direction intersecting with the first direction. The first power lines have lengths that extend from the second region to the first region, and the second power lines have lengths that extend from the third region to the first region.