Patents by Inventor Nam V. Dang
Nam V. Dang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130191679Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.Type: ApplicationFiled: March 15, 2012Publication date: July 25, 2013Applicant: QUALCOMM IncorporatedInventors: Jingcheng Zhuang, Nam V. Dang, Xiaohua Kong, Zhi Zhu, Tirdad Sowlati, Behnam Amelifard
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Publication number: 20130187717Abstract: A receiver equalization circuit includes a first output transistor having a gate coupled to an input signal. The receiver equalization circuit may also include a second output transistor having a drain coupled to a drain of the first output transistor. The receiver equalization circuit may also include a resistor coupled between a gate and a drain of the second output transistor to provide a direct current (DC) bias to the gate of the second output transistor. The receiver equalization circuit may further include a feed-through capacitor coupled between the gate of the second output transistor and an input signal source. The feed-through capacitor feeds the input signal to the gate of the second output transistor when a frequency of the input signal is above a predetermined threshold. The feed-through capacitor and the resistor define a signal gain amplification point.Type: ApplicationFiled: February 27, 2012Publication date: July 25, 2013Applicant: QUALCOMM IncorporatedInventors: Glenn A. Murphy, Nam V. Dang, Tirdad Sowlati, Xiaohua Kong
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Publication number: 20130187708Abstract: A pulse width modulated (PWM) signal is received and, over a time interval of the PWM signal, a first count is incremented when the PWM signal is at a first level, and a second count is incremented when the PWM signal is at a second level. At the end of time interval the first count is compared to the second count and, based on the comparison, a decoded bit is generated. Optionally, incrementing the first count is by enabling a first oscillator that increments a first counter, and incrementing the second count is by enabling a second oscillator that increments a second counter.Type: ApplicationFiled: May 11, 2012Publication date: July 25, 2013Applicant: QUALCOMM INCORPORATEDInventors: Nam V. Dang, Terrence B. Remple, Zhiqin Chen
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Publication number: 20130120071Abstract: A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning voltage. The tuning voltage range extension circuit is configured to selectively change current supplied by the first path as the tuning voltage exceeds a capacity threshold of the first transistor.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: QUALCOMM INCORPORATEDInventors: Swarna L. Navubothu, Cheng Zhong, Nam V. Dang, Xiaohua Kong
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Publication number: 20130120040Abstract: A method includes tracking a tuning voltage at a first circuit coupled to a first drain node of a first supply of a charge pump. The method also includes tracking the tuning voltage at a second circuit coupled to a second drain node of a second supply of the charge pump. The method further includes stabilizing a first voltage of the first drain node and a second voltage of the second drain node responsive to the tuning voltage.Type: ApplicationFiled: November 10, 2011Publication date: May 16, 2013Applicant: QUALCOMM INCORPORATEDInventors: Cheng Zhong, Swarna L. Navubothu, Nam V. Dang, Xiaohua Kong
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Publication number: 20130120020Abstract: An adjustable gain line driver receives an input signal and a gain control signal and outputs a signal with a swing, and the swing is measured to generate a swing measurement signal. A target swing signal is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal. The swing measurement signal is compared to the target swing reference control signal and a counter generating the gain control signal is incremented until the measurement signal meets the target swing reference signal. Optionally a reset signal resets the counter, and the gain control signal, at predetermined events.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: QUALCOMM INCORPORATEDInventors: Miao Li, Behnam Amelifard, Xiaohua Kong, Nam V. Dang
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Publication number: 20130120036Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.Type: ApplicationFiled: February 1, 2012Publication date: May 16, 2013Applicant: QUALCOMM IncorporatedInventors: Zhi Zhu, Xiaohua Kong, Nam V. Dang
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Publication number: 20130120029Abstract: In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: QUALCOMM INCORPORATEDInventors: Miao Li, Zhi Zhu, Xiaohua Kong, Nam V. Dang
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Publication number: 20130120072Abstract: A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.Type: ApplicationFiled: November 15, 2011Publication date: May 16, 2013Applicant: QUALCOMM INCORPORATEDInventors: Glenn A. Murphy, Xiaohua Kong, Nam V. Dang
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Publication number: 20130120028Abstract: A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: QUALCOMM INCORPORATEDInventors: Miao Li, Xiaohua Kong, Nam V. Dang
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Publication number: 20130033287Abstract: A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor.Type: ApplicationFiled: August 3, 2011Publication date: February 7, 2013Applicant: QUALCOMM INCORPORATEDInventors: Miao Li, Nam V. Dang, Xiaohua Kong
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Publication number: 20130030767Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Applicant: QUALCOMM IncorporatedInventors: Miao Li, Xiaohua Kong, Nam V. Dang, Cheng Zhong
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Patent number: 8289090Abstract: An amplitude control circuit includes a pair of peak detectors. The pair of peak detectors are responsive to a voltage reference generator. The amplitude control circuit is configured to be responsive to an oscillating signal of a crystal oscillator and configured to generate a control signal to control an amplitude of the oscillating signal.Type: GrantFiled: September 21, 2010Date of Patent: October 16, 2012Assignee: QUALCOMM IncorporatedInventors: Zhiqin Chen, Nam V. Dang, Nan Chen, Thuan Ly
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Publication number: 20120112809Abstract: In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path.Type: ApplicationFiled: November 4, 2010Publication date: May 10, 2012Applicant: QUALCOMM IncorporatedInventors: Zhi Zhu, Xiaohua Kong, Nam V. Dang
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Publication number: 20120109356Abstract: In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.Type: ApplicationFiled: November 3, 2010Publication date: May 3, 2012Applicant: QUALCOMM INCORPORATEDInventors: Xiaohua Kong, Zhi Zhu, Nam V. Dang, Tirdad Sowlati
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Publication number: 20120068774Abstract: An amplitude control circuit includes a pair of peak detectors. The pair of peak detectors are responsive to a voltage reference generator. The amplitude control circuit is configured to be responsive to an oscillating signal of a crystal oscillator and configured to generate a control signal to control an amplitude of the oscillating signal.Type: ApplicationFiled: September 21, 2010Publication date: March 22, 2012Applicant: QUALCOMM INCORPORATEDInventors: Zhiqin Chen, Nam V. Dang, Nan Chen, Thuan Ly
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Publication number: 20110084685Abstract: Power saving for hot plug detect (HPD) is disclosed. In a particular embodiment, a method includes detecting, at a source device that is connectable to a sink device, a connection of the source device to the sink device via a connector. The source device includes a DC voltage source and the connection is detected without consuming power from the DC voltage source.Type: ApplicationFiled: October 8, 2009Publication date: April 14, 2011Applicant: QUALCOMM IncorporatedInventors: Cheng Zhong, Nam V. Dang, Hung Q. Vuong, Xiaohua Kong
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Wideband tuning circuit for low-voltage silicon process and method for generating a tuning frequency
Publication number: 20030207672Abstract: A wideband tuning circuit suitable for a low-voltage silicon process includes a plurality of frequency band modules for generating a frequency within a particular frequency band of the tuning range. Each frequency band module includes a tuning sensitivity controller responsive to a tuning sensitivity control signal, a sub-band tuning network responsive to one of the frequency band module control signals, a resonator inductor, and a negative resistance generator coupled to the inductor to offset resistance of the inductor. A frequency band module control signal causes the sub-band tuning network to select a sub-band within the frequency band of one of the frequency band module, and a tuning sensitivity control signal causes the tuning sensitivity controller to control the output frequency of the frequency band module within a selected sub-band. A multiplexer selectively couples the output frequency from one of the frequency band modules in response to a band select signal.Type: ApplicationFiled: May 3, 2002Publication date: November 6, 2003Applicant: Intel CorporationInventors: Nam V. Dang, Thomas G. Egan -
Patent number: 5949472Abstract: A method of tuning channels for television and community antenna television (CATV) devices includes the step of receiving a radio frequency input (RFI) signal having at least one carrier signal at frequency f.sub.s associated with a selected broadcast channel. The RFI signal is up-converted by m to a first intermediate frequency wherein the carrier signal is located at f.sub.s +m. The first intermediate frequency is filtered. The filtered first intermediate frequency is down-converted by n to a second intermediate frequency wherein the second intermediate frequency includes the carrier signal at f.sub.s +m-n. Additional methods for improving the reception of the selected channel include the step of varying m and n in order to avoid frequency-dependent anomalies within the pass band of the filter. For digital communications, m and n are varied in accordance with an error rate of the digital communications in order to reduce the error rate of the digital communications.Type: GrantFiled: December 10, 1996Date of Patent: September 7, 1999Assignee: Intel CorporationInventors: Nam V. Dang, Lewis E. Adams, III