Abstract: The present invention relates to a method for manufacturing processed cork chips, and a floor construction method using the same. The processed cork chips are manufactured by the method, including: crushing and drying cork chips; adding polyurea to the dried cork chips to prepare a mixture; heating the mixture to cure the same; and cooling the cured mixture. Further, the floor construction method includes: laying the processed cork chips on the surface of a floor formed of concrete, a water-permeable base layer or crushed stone with a solidified top surface; and flattening the processed cork chips and pressing the same by means of a roller at a fixed temperature.

Abstract: The present invention relates to a method for manufacturing processed cork chips, and a floor construction method using the same. The processed cork chips are manufactured by the method, including: crushing and drying cork chips; adding polyurea to the dried cork chips to prepare a mixture; heating the mixture to cure the same; and cooling the cured mixture. Further, the floor construction method includes: laying the processed cork chips on the surface of a floor formed of concrete, a water-permeable base layer or crushed stone with a solidified top surface; and flattening the processed cork chips and pressing the same by means of a roller at a fixed temperature.

Abstract: A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, a first trench penetrating the dielectric layer on the isolation layer to separate parts of the dielectric layer, a second trench formed on the isolation layer and expanded from the first trench, and a second conductive layer formed over the dielectric layer to fill the first and second trenches.

Abstract: A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, the dielectric layer having a groove for exposing the isolation layer, a trench formed on the isolation layer and exposed through the groove, and a second conductive layer formed over the dielectric layer the trench.