Abstract: A bolting structure of a sub-frame includes a reinforcer mounting the sub-frame through a side member. The reinforcer includes: a reinforcing member disposed to intersect with the side member in a cross shape and bolted, together with the side member, to a lower panel; an inner pipe disposed at the side member from surfaces interfacing between the reinforcing member and the side member; an outer pipe disposed at the reinforcing member from the surfaces interfacing between the reinforcing member and the side member and inserted into the sub-frame; and a bolt bolted to the inner pipe through the outer pipe and fixing the sub-frame.

Abstract: According to example embodiments of inventive concepts: a semiconductor device includes: first and second trench gates extending long in one direction in a substrate; third and fourth trench gates in the substrate, the third and fourth trench gates connecting the first and second trench gates with each other; a first region defined in the substrate by the first to fourth trench gates and surrounded by the first to fourth trench gates; and a second region and a third region defined in the substrate. The second region is in surface contact with the first region. The third region is in point contact with the first region. The first region includes a first high-voltage semiconductor device including a body of a first conduction type and an emitter of a second conduction type in the body. Floating wells of the first conduction type are in the second region and the third region.

Abstract: A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.

Abstract: A semiconductor device comprises a substrate and a gate which extends on the substrate in a first horizontal direction. A source region is positioned at a first side of the gate and extends in the first direction. A body region of a first conductivity type is under the source region and extends in the first direction. A drain region of a second conductivity type is at a second side of the gate and extends in the first direction. A drift region of the second conductivity type extends between the body region and the drain region in the substrate in a second horizontal direction. A first buried layer is under the drift region in the substrate, the first buried layer extending in the first and second directions. A plurality of second buried layers is between the first buried layer and the drift region in the substrate. The second buried layers extend in the second direction and are spaced apart from each other in the first direction.

Abstract: Provided is a manufacturing method for an insulated-gate bipolar transistor (IGBT). The manufacturing method includes providing a structure including a substrate, a first conductivity type epitaxial layer formed on the substrate, a gate electrode formed on a first surface of the epitaxial layer, a second conductivity type body region formed at opposite sides of the gate electrode in the first surface of the epitaxial layer, and a first conductivity type source region formed within the body region; removing a portion of the substrate by back grinding; and removing the other portion of the substrate by etching until the second surface of the epitaxial layer is exposed.

Abstract: A semiconductor device comprises a substrate and a gate which extends on the substrate in a first horizontal direction. A source region is positioned at a first side of the gate and extends in the first direction. A body region of a first conductivity type is under the source region and extends in the first direction. A drain region of a second conductivity type is at a second side of the gate and extends in the first direction. A drift region of the second conductivity type extends between the body region and the drain region in the substrate in a second horizontal direction. A first buried layer is under the drift region in the substrate, the first buried layer extending in the first and second directions. A plurality of second buried layers is between the first buried layer and the drift region in the substrate. The second buried layers extend in the second direction and are spaced apart from each other in the first direction.

Abstract: Disclosed are a method of managing a process and a process managing system in which a failure-generating process step can be quickly detected. The method of managing a process includes sequentially performing first to n-th (n is a natural number) process steps with respect to a plurality of wafers, the order that the plurality of wafers are processed in each of the n process steps are different from one another. Calculating characteristic parameter values for the plurality of wafers, calculating first to n-th relations that indicate relationships between the first to n-th process orders and the characteristic parameter values, performing a Fourier transform on the first to n-th relations so as to calculate first to n-th conversion relations, and determining the existence of patterns among the first to n-th relations using the first to n-th conversion relations.

Abstract: A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.

Abstract: A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.

Abstract: Disclosed are a method of managing a process and a process managing system in which a failure-generating process step can be quickly detected. The method of managing a process includes sequentially performing first to n-th (n is a natural number) process steps with respect to a plurality of wafers, the order that the plurality of wafers are processed in each of the n process steps are different from one another. Calculating characteristic parameter values for the plurality of wafers, calculating first to n-th relations that indicate relationships between the first to n-th process orders and the characteristic parameter values, performing a Fourier transform on the first to n-th relations so as to calculate first to n-th conversion relations, and determining the existence of patterns among the first to n-th relations using the first to n-th conversion relations.