Abstract: A time centering module cooperates with an image sensor that is configured to capture two or more image captures at least one of 1) several different lengths of exposures of a same subject matter, 2) several different integration times for that same subject matter, and 3) any combination of these, that are to be merged into a High Dynamic Range (HDR) image capture. The time centering module is also configured to cooperate with data storage components. The time centering module correlates image data of a moving object from the two or more image captures stored in the data storage component. The image captures each have different integration times in a rolling shutter or different lengths of exposures in a global shutter in order to correlate the image data of the moving object in image captures by a midpoint in time of their respective image capture.

Abstract: In general, the disclosure describes a sensor comprising a photo-sensitive silicon substrate configured to detect ultraviolet (UV), visible, and near-infrared (NIR) light and an upconversion layer comprising a plurality of crystals configured to convert short wave infrared light to UV, visible, or NIR light. An example sensor includes an upconversion layer comprising a plurality of crystals configured to convert electromagnetic radiation comprising a first range of wavelengths greater than 1100 nm to electromagnetic radiation comprising a second range of wavelengths less than or equal to 1100 nm and a photo-sensitive silicon substrate configured to detect the electromagnetic radiation comprising the second range of wavelengths.

Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.

Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.

Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.

Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.

Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.

Abstract: A method of forming an array of photodiodes includes forming a cap layer on a surface of an absorption layer. The method includes forming a plurality of spaced apart pixel diffusion areas in the cap layer. The method includes forming a mesa trench with opposed sidewalls through the cap layer, wherein the mesa trench surrounds each of the pixel diffusion areas separating the pixel diffusion areas from one another. The method includes forming a sidewall passivation layer over the sidewalls of the mesa trench and removing a portion of the sidewall passivation layer to expose a respective contact electrically connected to each of the pixel diffusion areas, but leaving the sidewalls of the mesa trench covered with the sidewall passivation layer wherein the contact is open and uncovered for electrical connection.

Abstract: A photodiode includes an absorption layer. A cap layer is disposed on a surface of the absorption layer. A pixel diffusion area within the cap layer extends beyond the surface of the absorption layer and into the absorption layer to receive a charge generated from photons therefrom. A mesa trench is defined through the cap layer surrounding the pixel diffusion area, wherein the mesa trench defines a floor at the surface of the absorption layer and opposed sidewalls extending away from the surface of the absorption layer. An implant is aligned with the mesa trench and extends from the floor of the mesa trench through the absorption layer surrounding a portion of the absorption layer proximate the pixel diffusion area.

Abstract: A photodiode includes an absorption layer. A cap layer is disposed on a surface of the absorption layer. A pixel diffusion area within the cap layer extends beyond the surface of the absorption layer and into the absorption layer to receive a charge generated from photons therefrom. A mesa trench is defined through the cap layer surrounding the pixel diffusion area, wherein the mesa trench defines a floor at the surface of the absorption layer and opposed sidewalls extending away from the surface of the absorption layer. An implant is aligned with the mesa trench and extends from the floor of the mesa trench through the absorption layer surrounding a portion of the absorption layer proximate the pixel diffusion area.

Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.

Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.

Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.

Abstract: Gas phase nucleation conditions are controlled and/or mitigated during material deposition in semiconductor manufacturing processes. According to an example embodiment of the present invention, reaction by-product gases are monitored (e.g., 140, 160) and used to detect reactant gas conditions that promote gas phase nucleation. In some applications, an optical detection approach (e.g., 140, 142) is used to detect the presence of the reaction by-product gases, and relative amounts of the gases are used as an indicator of a ratio of reactant gases (e.g., 310, 340); the supply of reactant gases and/or other deposition conditions are correspondingly controlled (e.g., 130-138, via 160).

Abstract: A method of forming an non-oxide thin film includes introducing a work function reducing agent onto a surface of a sputter target facing into a substrate in a process chamber, providing an inert gas into the process chamber, ionizing the inert gas, thereby generating a plurality of electrons, disintegrating a plurality of negatively charged ions from the sputter target, and forming the non-oxide thin film on the substrate from the negatively charged ions.

Abstract: A method of forming an oxide thin film includes introducing a work function reducing agent onto a surface of a sputter target facing into a substrate in a process chamber, providing an oxygen gas and an inert gas into the process chamber, ionizing the oxygen gas and the inert gas, thereby generating a plurality of electrons, disintegrating a plurality of negatively charged ions from the sputter target, and forming the oxide thin film on the substrate from the negatively charged ions reacted with the ionized oxygen gas.