Abstract: A multi-stage sense amplifier for read-only memory having a memory array consisting of a large number of memory cell units. The sense amplifier includes a sense amplifier for sensing the currents flowing through the transistor of the memory cell units of the read-only memory. The memory cell unit transistors are programmed with one of four current capacity characteristics. The sense amplifier also includes three current comparators coupled to the sense amplifier, with each of the comparators having a current comparing unit for comparing the sensed current flowing through the memory cell unit transistors to the current flowing through the comparators. An output of each of the three comparators is provided for identifying whether or not the current of a four capacity characteristics flowing through the memory cell unit transistors is larger than the current flowing through the comparator.

Abstract: A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon substrate. Each memory cell consists of a transistor element and a diode element electrically connected in series. Each transistor element has a drain layer, a channel layer, a source layer all stacked on the silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on the silicon substrate. The gate electrode regions and the upright drain/channel/source structure regions of the transistor elements are alternately arranged in an adjacent fashion along a substantially horizontal direction. Each diode element is formed by one upright drain/channel/source structure and a diode layer formed on or under the upright drain/channel/source structure.

Abstract: A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon substrate. Each memory cell consists of a transistor element and a diode element electrically connected in series. Each transistor element has a drain layer, a channel layer, a source layer all stacked on the silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on the silicon substrate. The gate electrode regions and the upright drain/channel/source structure regions of the transistor elements are alternately arranged in an adjacent fashion along a substantially horizontal direction. Each diode element is formed by one upright drain/channel/source structure and a diode layer formed on or under the upright drain/channel/source structure.