Abstract: A method and apparatus for confirming the operation of memory (212) operates during periods when the memory is not operating in a standard execution mode. This strategy allows the memory to be checked real-time without impacting normal bandwidth of an associated CPU (200). The method and apparatus guarantees deterministic testing by including circuitry and steps which force bus mastership and, therefore, memory access if the memory is busy for too long a period of time.

Abstract: A method and apparatus for confirming the operation of memory (212) operates during periods when the memory is not operating in a standard execution mode. This strategy allows the memory to be checked real-time without impacting normal bandwidth of an associated CPU (200). The method and apparatus guarantees deterministic testing by including circuitry and steps which force bus mastership and, therefore, memory access if the memory is busy for too long a period of time.

Abstract: A digital timer apparatus incorporates a free running counter, an interval timer, a capture register, a pulse accumulator; holding logic and mode selection logic. In one mode of operation, a rising or falling edge of an external signal causes the current contents of the free running counter to be loaded into the capture register, causes the previous value of the capture register to be transferred to a holding register and causes the pulse accumulator to be incremented. A read of the capture holding register causes the pulse accumulator value to be transferred to a holding register and causes the pulse accumulator to be reset. The output of the interval timer can cause an interrupt signal to be generated to request service from a central processing unit.

Abstract: A register having a selective wait feature includes logic for receiving a new value to be stored and logic for selectively delaying the appearance of the new value at the output of the register until some predetermined event has occurred. The register can also be read to determine whether the event has occurred. The register is disclosed in the context of a microprocessor-controlled digital timer apparatus which responds to an incoming pulse train. Certain control bits in the apparatus determine whether the digital timer is responsive to rising edges of the pulse train, falling edges, any edges, or no edges. The microprocessor determines, at the time new values are stored to those control bit locations, whether the new values are to become effective immediately or are to be delayed until some intervening event has occurred. The register permits control over the time at which transitions between different operating modes are made in order to assure orderly operation.