Patents by Inventor Nancy Y. Zhou

Nancy Y. Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic microprocessor gate design tool for area/timing margin control
    Patent number: 10671791
    Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
  • DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL
    Publication number: 20180330039
    Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 15, 2018
    Inventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
  • Dynamic microprocessor gate design tool for area/timing margin control
    Patent number: 10078722
    Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: September 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
  • DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL
    Publication number: 20170357747
    Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou