Abstract: A wireless radio-frequency transmission apparatus includes a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator. The twin voltage-controlled oscillator includes a first oscillator and a second oscillator. When the twin voltage-controlled oscillator is in a reception mode, the first and the second oscillators are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers. When the twin voltage-controlled oscillator is in a transmission mode, the first oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop, and the second oscillator performs frequency modulation on transmitted data.

Abstract: The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (102), a loop filter (103) parameter, a multi-path voltage-controlled oscillator (104) and a first multiplexer (105) corresponding thereto, a five-stage-division-by-two frequency division link (109) and a corresponding second multiplexer (110) and third multiplexer (112), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

Abstract: The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

Abstract: The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

Abstract: The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (102), a loop filter (103) parameter, a multi-path voltage-controlled oscillator (104) and a first multiplexer (105) corresponding thereto, a five-stage-division-by-two frequency division link (109) and a corresponding second multiplexer (110) and third multiplexer (112), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

Abstract: The present disclosure discloses a wireless radio-frequency transmission apparatus, comprising: a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator, wherein the twin voltage-controlled oscillator comprises a first voltage-controlled oscillator and a second voltage-controlled oscillator which are of the same structure, wherein when the twin voltage-controlled oscillator is in a reception mode, the first voltage-controlled oscillator and the second voltage-controlled oscillator are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers for receiving information; and when the twin voltage-controlled oscillator is in a transmission mode, the first voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop,

Abstract: The present invention proposes a dynamically reconfigurable multi-level parallel single instruction multiple data array processing system which has a pixel level parallel image processing element array and a row-parallel array processor. The PE array mainly implements a linear operation which is adapted to be executed in parallel in the low and middle levels of image processing and the RP array implements an operation which is adapted to execute in row-parallel in the low and middle levels of image processing or more complex nonlinear operations.

Abstract: The present invention proposes a dynamically reconfigurable multistage parallel single instruction multiple data array processing system which has a pixel level parallel image processing element array and a row processor array parallel. The PE array mainly implements a linear operation which is adapted to be executed in parallel in the low and middle levels of image processing and the RP array implements an operation which is adapted to be executed in row-parallel in the low and middle levels of image processing or more complex nonlinear operations.