Abstract: Performance of a semiconductor device is improved. An active cell region has a first gate electrode that extends in a Y direction and receives a gate potential, and a second gate electrode that extends in the Y direction and receives an emitter potential. A hybrid cell region including a p-type base region and an n-type emitter region is disposed in the active cell region. An n-type isolation region adjacent to the hybrid cell region in the Y direction is formed in the active cell region excluding the hybrid cell region. Hence, even if the p-type base region or a p-type floating region is formed in the active cell region excluding the hybrid cell region, such a p-type region is isolated from the base region in the hybrid cell region by the isolation region.

Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.

Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third trench gate electrodes located on both sides of the first trench gate electrode interposed therebetween. In each of a semiconductor layer located between the first and second trench gate electrodes and the semiconductor layer located between the first and third trench gate electrodes, a plurality of p+-type semiconductor regions are formed. The p+-type semiconductor regions are arranged along the extending direction of the first trench gate electrode in plan view to be spaced apart from each other.

Abstract: A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

Abstract: A semiconductor device includes a first trench gate electrode and a second trench gate electrode which are electrically connected to a gate electrode, and a third trench gate electrode and a fourth trench gate electrode which are electrically connected to an emitter electrode. A plurality of p+ type semiconductor regions are formed in a part of a semiconductor layer between the first trench gate electrode and the second trench gate electrode. The plurality of p+ type semiconductor regions are arranged to be spaced apart from each other along an extending direction of the first trench gate electrode when seen in a plan view.

Abstract: An improvement is achieved in the IE effect of a semiconductor device including an IGBT having an active cell region with an EGE structure. Each of a plurality of hybrid cell regions extending in a Y-axis direction has first, second, and third trench electrodes extending in the Y-axis direction, a p-type body region, and contact trenches provided between the first and second trench electrodes and between the first and third trench electrodes to extend in the Y-axis direction and reach middle points in the p-type body region. Each of the hybrid cell regions further has a plurality of n+-type emitter regions formed in an upper surface of a semiconductor substrate located between the contact trenches and the first trench electrode to be shallower than the contact trenches and spaced apart at regular intervals in the Y-direction in plan view. The n+-type emitter regions are arranged in a staggered configuration in plan view.

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

Abstract: A power conversion device includes a high-side transistor including an IGBT, a low-side transistor including an IGBT, and having a collector coupled to an emitter of the high-side transistor, a high-side driver configured to drive the high-side transistor; and a low-side driver configured to drive the low-side transistor, wherein each of the high-side transistor and the low-side transistor includes a first trench gate electrode arranged in an active cell region, and electrically connected to a gate, and a second trench gate electrode and a third trench gate electrode, each of which is arranged at intervals on both sides of the first trench gate electrode, and electrically connected to the emitter in the active cell region. The high-side driver includes a first pull-up transistor configured to apply a first voltage as a positive voltage to the gate, based on the emitter of the high-side transistor and a first pull-down transistor.

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

Abstract: An improvement is achieved in the IE effect of a semiconductor device including an IGBT having an active cell region with an EGE structure. Each of a plurality of hybrid cell regions extending in a Y-axis direction has first, second, and third trench electrodes extending in the Y-axis direction, a p-type body region, and contact trenches provided between the first and second trench electrodes and between the first and third trench electrodes to extend in the Y-axis direction and reach middle points in the p-type body region. Each of the hybrid cell regions further has a plurality of n+-type emitter regions formed in an upper surface of a semiconductor substrate located between the contact trenches and the first trench electrode to be shallower than the contact trenches and spaced apart at regular intervals in the Y-direction in plan view. The n+-type emitter regions are arranged in a staggered configuration in plan view.

Abstract: To reduce the number of mounted components in the power conversion device and drive device. Each high-side transistor and low-side transistor has an EGE-type structure of (emitter-gate-emitter type). A high-side driver includes a first pull-up transistor configured to apply a first positive voltage to a gate based on an emitter of the high-side transistor, and a first pull-down transistor configured to couple the gate to the emitter. A low-side driver includes a second pull-up transistor configured to apply a second positive voltage to the gate based on an emitter of the low-side transistor, and a second pull-down transistor configured to couple the gate to the emitter.

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

Abstract: A semiconductor device includes a first trench gate electrode and a second trench gate electrode which are electrically connected to a gate electrode, and a third trench gate electrode and a fourth trench gate electrode which are electrically connected to an emitter electrode. A plurality of p+ type semiconductor regions are formed in a part of a semiconductor layer between the first trench gate electrode and the second trench gate electrode. The plurality of p+ type semiconductor regions are arranged to be spaced apart from each other along an extending direction of the first trench gate electrode when seen in a plan view.

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third trench gate electrodes located on both sides of the first trench gate electrode interposed therebetween. In each of a semiconductor layer located between the first and second trench gate electrodes and the semiconductor layer located between the first and third trench gate electrodes, a plurality of p+-type semiconductor regions are formed. The p+-type semiconductor regions are arranged along the extending direction of the first trench gate electrode in plan view to be spaced apart from each other.

Abstract: A semiconductor device includes a first trench gate electrode and a second trench gate electrode which are electrically connected to a gate electrode, and a third trench gate electrode and a fourth trench gate electrode which are electrically connected to an emitter electrode. A plurality of p+ type semiconductor regions are formed in a part of a semiconductor layer between the first trench gate electrode and the second trench gate electrode. The plurality of p+ type semiconductor regions are arranged to be spaced apart from each other along an extending direction of the first trench gate electrode when seen in a plan view.

Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third trench gate electrodes located on both sides of the first trench gate electrode interposed therebetween. In each of a semiconductor layer located between the first and second trench gate electrodes and the semiconductor layer located between the first and third trench gate electrodes, a plurality of p+-type semiconductor regions are formed. The p+-type semiconductor regions are arranged along the extending direction of the first trench gate electrode in plan view to be spaced apart from each other.

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

Abstract: To reduce the number of mounted components in the power conversion device and drive device. Each high-side transistor and low-side transistor has an EGE-type structure of (emitter-gate-emitter type). A high-side driver includes a first pull-up transistor configured to apply a first positive voltage to a gate based on an emitter of the high-side transistor, and a first pull-down transistor configured to couple the gate to the emitter. A low-side driver includes a second pull-up transistor configured to apply a second positive voltage to the gate based on an emitter of the low-side transistor, and a second pull-down transistor configured to couple the gate to the emitter.