Patents by Inventor Naoaki Yamanaka

Naoaki Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5878029
    Abstract: When bandwidth in an ATM network is controlled so as to increase in accordance with a user request, there is a considerable delay from the occurrence of the request until the bandwidth is actually changed; and there is therefore a need to control the traffic flowing in ATM network transmission paths faster and more flexibly. There is also a need to decrease the probability of overbooking occurring when deciding whether or not to accept a bandwidth change request. Route information that includes information relating to residual bandwidth is therefore collected in advance by subscriber switches that serve terminals. In response to a request from a user, a subscriber switch alone replies rapidly. During this process, the fact that there are a plurality of bandwidth change requests within the same residual bandwidth measurement period, is considered and a portion of the measured residual bandwidth is held for other bandwidth change requests. This enables the delay to be shortened.
    Type: Grant
    Filed: February 12, 1997
    Date of Patent: March 2, 1999
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Haruhisa Hasegawa, Naoaki Yamanaka, Kouhei Shiomoto
  • Patent number: 5828654
    Abstract: In an input cell policing method in a network of an asynchronous transfer mode, according to information contained in a header field of each input cell, a group to which the cell belongs is identified. For each group, there are set a plurality of time frames having a predetermined length and mutually different phases to count the number of input cells in each time frame period. For each time frame, the count value of input cells is compared with a predetermined threshold value. An input cell for which the count value exceeds the threshold value in either one of the time frames is assumed to be an excess cell. The excess cell is discarded or a violation mark is added thereto.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: October 27, 1998
    Assignees: Hitachi, Ltd., Nippon Telegraph & Telephone Corp.
    Inventors: Akihiko Takase, Shigeo Shinada, Mitsuhiro Takano, Toshiya Oouchi, Naoaki Yamanaka, Youichi Sato
  • Patent number: 5812532
    Abstract: In order to establish virtual channel networks on an ATM network, a different virtual channel handler interconnection network for each media or service consisting of information to be transferred is established on a virtual path network; and virtual channel networks corresponding to these media or services are formed by the respective virtual channel handler interconnection networks, whereby a plurality of independent virtual channel networks for different media or services are established simultaneously on a single physical network.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: September 22, 1998
    Assignee: Nippon Telegraph & Telephone Corporation
    Inventors: Eiji Oki, Naoaki Yamanaka
  • Patent number: 5577030
    Abstract: A device and method for designing a reliable communication network using disjoint paths with no shared links or nodes. An adjacency matrix is copied to a temporary adjacency matrix, and when it has been confirmed by matrix calculation that there is a path or paths between the origin and destination nodes, a path is obtained backwards and links in the path are deleted. The search for a path is repeated using the resulting temporary adjacency matrix. In this way, the actual number of disjoint paths is never overestimated. Rapid calculation is possible by means of a super-computer.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: November 19, 1996
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Eiji Oki, Naoaki Yamanaka
  • Patent number: 5509008
    Abstract: An ATM switch in which the throughput is improved by the simplified arbitration scheme and circuit configuration. This ATM switch uses a matrix type switch formed by N input lines for transmitting the cells read out from the input buffers, M output lines for transmitting the cells to be written into the output buffers, and N.times.M crosspoints located at intersections of the input lines and the output lines, where each crosspoint at an intersection of one input line and one output line carries out an arbitration operation in which a cell arriving from an upper stream side of that one output line is passed to a lower stream side of that one output line with a higher priority than a cell arriving from that one input line, and tile cell arriving from that one input line is transferred to the lower stream side of that one output line only when there is no cell arriving from the upper stream side of that one output line.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: April 16, 1996
    Assignee: Nippon Telegraph & Telephone Corp.
    Inventors: Kouichi Genda, Naoaki Yamanaka
  • Patent number: 5469543
    Abstract: In a policing arrangement for an ATM network, every incoming cell is stored in a cell buffer and a virtual path identifier (VPI) contained in the cell is extracted and translated to a corresponding one of a set of threshold values. Policing circuits of a matrix array are connected column by column for transferring a VPI in accordance with a read/write control circuit. Each policing circuit of the first column is uniquely responsive to a VPI of a particular value for storing the extracted VPI into a bridge memory, and this column has a greater number of policing circuits than any of the other columns of the array. In each column of the array, at least one of the policing circuits includes a cell counter for incrementing a cell count value in response to the VPI of every incoming cell and decrementing the cell count in response to a VPI read out of the bridge memory of the policing circuit.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: November 21, 1995
    Assignee: NEC Corporation
    Inventors: Motoo Nishihara, Takatoshi Kurano, Naoaki Yamanaka, Youichi Sato
  • Patent number: 5465348
    Abstract: A UPC circuit fault diagnosis system for diagnosing a failure in a UPC circuit controls cell traffic volume on the basis of prescribed information about cell traffic. Failure diagnosis of a UPC circuit is provided by a usage parameter determination of at least one kind of cell, using more than one system and comparing determination results. The diagnosis system has an operating UPC circuit for controlling a total of m kinds of cells, and a standby UPC circuit for controlling a total of n kinds of cells. The system also has a total of q bridge memories for keeping a chronological record of the prescribed information of arriving cells. A fault diagnosis of the bridge memories is provided by comparing the contents of the bridge memories, using more than one system.
    Type: Grant
    Filed: January 8, 1993
    Date of Patent: November 7, 1995
    Assignee: Fujitsu Limited
    Inventors: Shigeo Amemiya, Takao Ogura, Takafumi Chujo, Hiroshi Takeo, Michio Kusayanagi, Naoaki Yamanaka, Yoichi Sato, Akihiko Takase, Shigeo Shinada, Mituhiro Takano, Kiyoshi Saitou, Kazuhiko Hohara, Tetuhiro Okabe
  • Patent number: 5432713
    Abstract: A usage parameter control circuit for effecting a policing control in an ATM transmission network, comprising a time interval measuring unit for measuring a time interval between a current arrival time of a cell to be judged, and an arrival time of a cell which arrived a reference threshold number of cells before the currently arriving cell arrives; and a judging unit for judging whether or not the measured time interval is shorter than a reference threshold time interval, whereby a longer accessing time is allowed and the circuit construction has a flexible expandability.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: July 11, 1995
    Assignees: Fujitsu Limited, Nippon Telegraph and Telephone Corporation
    Inventors: Hiroshi Takeo, Michio Kusayanagi, Kazuo Iguchi, Naoaki Yamanaka, Youichi Sato
  • Patent number: 5394408
    Abstract: A policing control apparatus having a cell input terminal receiving asynchronous transmission communication network cells; a policing circuit coupled to the input terminal for policing transmission of cells according to policing information; a cell output terminal from the policing circuit for outputting policed cells; a count memory in the policing circuit for storing a count value of the cells supplied to the policing circuit and for supplying the count value as the policing information; and a self-diagnosing circuit for monitoring problems and abnormalities of stored contents in the count memory and outputting an alarm upon detection of a problem or abnormality.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: February 28, 1995
    Assignees: NEC Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Motoo Nishihara, Takatoshi Kurano, Naoaki Yamanaka, Youichi Sato
  • Patent number: 4788679
    Abstract: A packet switch has pluralities of incoming and outgoing trunks, a data memory accessible from them in common, and FIFO memories each provided in each of input and output circuits. Data from the incoming trunks is written into and read out from the buffer memory for transfer to the outgoing trunks, on a time-shared basis, to perform packet switching between trunks of different data transfer rates. Furthermore, the packet switch has an arbiter for detecting process requests from the input circuits and an arbiter for detecting process requests from the output circuits, so that priority control is effected for servicing the requests. As a result, dynamic allocation of access to the buffer memory to the input and output circuits is permitted.
    Type: Grant
    Filed: August 10, 1987
    Date of Patent: November 29, 1988
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hideki Kataoka, Tatsuro Takahashi, Shiro Kikuchi, Naoaki Yamanaka, Hajime Sakakibara, Miki Hirano