Patents by Inventor Naofumi Nakamura

Naofumi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110256672
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Makoto WADA, Kazuyuki HIGASHI, Naofumi NAKAMURA, Tsuneo UENAKA
  • Patent number: 8015851
    Abstract: When forming a dowel section by performing press working on each of portions constituting side walls of a buckle base member, a die having a negative clearance with a punch portion (2) is used whose length or diameter is larger than a length or diameter of a die portion (3). The dowel section is required as a guide for a tongue inserted into a buckle and as a load receiver when a latch member is elongated at a time of collision etc. When a ratio C/t of a clearance C between the punch portion and the die portion with respect to a plate thickness t of the buckle base member is set within a range of ?(30 to 5) %, no crack is generated in the root of the dowel section, and the dowel section of a shear cross-section length ?0.25×t, a shear cross-section starting height ?0.7×t, and a height of (0.70 to 0.95)×t is easily obtained, and the perpenducularity of the dowel section side surface is enhanced.
    Type: Grant
    Filed: December 25, 2006
    Date of Patent: September 13, 2011
    Assignees: Nisshin Steel Co., Ltd., Takata Corporation
    Inventors: Hirokazu Sasaki, Naofumi Nakamura, Shigeru Morikawa, Hideto Hashimoto, Takaaki Kimura, Yoshihiko Kawai
  • Patent number: 7994054
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Patent number: 7989880
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Kazuyuki Higashi, Naofumi Nakamura, Tsuneo Uenaka
  • Patent number: 7902068
    Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayoshi Watanabe, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu
  • Patent number: 7791202
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Patent number: 7786589
    Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first dielectric film, a metal ring provided in the first dielectric film and the second dielectric film and configured to form a closed loop in a plan view, a first region surrounded by the metal ring in a plan view, a second region provided outside of the metal ring in a plan view, a plurality of via contacts provided in the first dielectric film in the first and second region, a plurality of wirings provided in the second dielectric film in the first and second region, and an air gap provided in the second dielectric film in the first region.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: August 31, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noriaki Matsunaga, Yoshiaki Shimooka, Naofumi Nakamura
  • Publication number: 20100213526
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Application
    Filed: November 10, 2009
    Publication date: August 26, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Kazuyuki HIGASHI, Naofumi NAKAMURA, Tsuneo UENAKA
  • Patent number: 7691740
    Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: April 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiko Yoshizawa, Noriaki Matsunaga, Naofumi Nakamura
  • Publication number: 20090042358
    Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.
    Type: Application
    Filed: October 14, 2008
    Publication date: February 12, 2009
    Inventors: Takahiko YOSHIZAWA, Noriaki Matsunaga, Naofumi Nakamura
  • Publication number: 20090019911
    Abstract: When forming a dowel section by performing press working on each of portions constituting side walls of a buckle base member, a die of a negative clearance with a punch portion (2) is used whose length or diameter is larger than a length or diameter of a die portion (3), the dowel section being required as a guide for a tongue inserted into a buckle and as a load receiver when a latch member is elongated at a time of collision etc. When a ratio C/t of a clearance C between the punch portion and the die portion with respect to a plate thickness t of the buckle base member is set within a range of ?(30 to 5)%, no crack is generated in the root of the dowel section, and the dowel section of a shear cross-section length ?0.25×t, a shear cross-section starting height ?0.7×t, and a height of (0.70 to 0.95)×t is easily obtained, and the perpenducularity of the dowel section side surface is enhanced.
    Type: Application
    Filed: December 25, 2006
    Publication date: January 22, 2009
    Inventors: Hirokazu Sasaki, Naofumi Nakamura, Shigeru Morikawa, Hideto Hashimoto, Takaaki Kimura, Yoshihiko Kawai
  • Publication number: 20080311742
    Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.
    Type: Application
    Filed: December 19, 2007
    Publication date: December 18, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tadayoshi WATANABE, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu
  • Publication number: 20080296775
    Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first dielectric film, a metal ring provided in the first dielectric film and the second dielectric film and configured to form a closed loop in a plan view, a first region surrounded by the metal ring in a plan view, a second region provided outside of the metal ring in a plan view, a plurality of via contacts provided in the first dielectric film in the first and second region, a plurality of wirings provided in the second dielectric film in the first and second region, and an air gap provided in the second dielectric film in the first region.
    Type: Application
    Filed: December 6, 2007
    Publication date: December 4, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Noriaki Matsunaga, Yoshiaki Shimooka, Naofumi Nakamura
  • Patent number: 7459391
    Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: December 2, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiko Yoshizawa, Noriaki Matsunaga, Naofumi Nakamura
  • Publication number: 20080261398
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Application
    Filed: January 24, 2008
    Publication date: October 23, 2008
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Publication number: 20080122102
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Application
    Filed: January 24, 2008
    Publication date: May 29, 2008
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Publication number: 20080090410
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.
    Type: Application
    Filed: August 30, 2007
    Publication date: April 17, 2008
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Patent number: 7351656
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: April 1, 2008
    Assignee: Kabushiki Kaihsa Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Patent number: 7339256
    Abstract: A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: March 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naofumi Nakamura, Noriaki Matsunaga, Sachiyo Ito, Masahiko Hasunuma, Takeshi Nishioka
  • Patent number: 7169697
    Abstract: Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the wiring layer equal to the first wiring structure and including a second plug and a second wiring formed on the second plug, wherein the upper surface of the first wiring is positioned higher than the upper surface of the second wiring, and the lower surface of the first wiring is positioned flush with or lower than the upper surface of the second wiring. The present invention also provides a method of manufacturing the particular semiconductor device.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: January 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoji Seta, Makoto Sekine, Naofumi Nakamura