Patents by Inventor Naofumi Nakamura
Naofumi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110256672Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Makoto WADA, Kazuyuki HIGASHI, Naofumi NAKAMURA, Tsuneo UENAKA
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Patent number: 8015851Abstract: When forming a dowel section by performing press working on each of portions constituting side walls of a buckle base member, a die having a negative clearance with a punch portion (2) is used whose length or diameter is larger than a length or diameter of a die portion (3). The dowel section is required as a guide for a tongue inserted into a buckle and as a load receiver when a latch member is elongated at a time of collision etc. When a ratio C/t of a clearance C between the punch portion and the die portion with respect to a plate thickness t of the buckle base member is set within a range of ?(30 to 5) %, no crack is generated in the root of the dowel section, and the dowel section of a shear cross-section length ?0.25×t, a shear cross-section starting height ?0.7×t, and a height of (0.70 to 0.95)×t is easily obtained, and the perpenducularity of the dowel section side surface is enhanced.Type: GrantFiled: December 25, 2006Date of Patent: September 13, 2011Assignees: Nisshin Steel Co., Ltd., Takata CorporationInventors: Hirokazu Sasaki, Naofumi Nakamura, Shigeru Morikawa, Hideto Hashimoto, Takaaki Kimura, Yoshihiko Kawai
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Patent number: 7994054Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.Type: GrantFiled: August 30, 2007Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Patent number: 7989880Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.Type: GrantFiled: November 10, 2009Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Wada, Kazuyuki Higashi, Naofumi Nakamura, Tsuneo Uenaka
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Patent number: 7902068Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.Type: GrantFiled: December 19, 2007Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tadayoshi Watanabe, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu
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Patent number: 7791202Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.Type: GrantFiled: January 24, 2008Date of Patent: September 7, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Patent number: 7786589Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first dielectric film, a metal ring provided in the first dielectric film and the second dielectric film and configured to form a closed loop in a plan view, a first region surrounded by the metal ring in a plan view, a second region provided outside of the metal ring in a plan view, a plurality of via contacts provided in the first dielectric film in the first and second region, a plurality of wirings provided in the second dielectric film in the first and second region, and an air gap provided in the second dielectric film in the first region.Type: GrantFiled: December 6, 2007Date of Patent: August 31, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Noriaki Matsunaga, Yoshiaki Shimooka, Naofumi Nakamura
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Publication number: 20100213526Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.Type: ApplicationFiled: November 10, 2009Publication date: August 26, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto WADA, Kazuyuki HIGASHI, Naofumi NAKAMURA, Tsuneo UENAKA
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Patent number: 7691740Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.Type: GrantFiled: October 14, 2008Date of Patent: April 6, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takahiko Yoshizawa, Noriaki Matsunaga, Naofumi Nakamura
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Publication number: 20090042358Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.Type: ApplicationFiled: October 14, 2008Publication date: February 12, 2009Inventors: Takahiko YOSHIZAWA, Noriaki Matsunaga, Naofumi Nakamura
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Publication number: 20090019911Abstract: When forming a dowel section by performing press working on each of portions constituting side walls of a buckle base member, a die of a negative clearance with a punch portion (2) is used whose length or diameter is larger than a length or diameter of a die portion (3), the dowel section being required as a guide for a tongue inserted into a buckle and as a load receiver when a latch member is elongated at a time of collision etc. When a ratio C/t of a clearance C between the punch portion and the die portion with respect to a plate thickness t of the buckle base member is set within a range of ?(30 to 5)%, no crack is generated in the root of the dowel section, and the dowel section of a shear cross-section length ?0.25×t, a shear cross-section starting height ?0.7×t, and a height of (0.70 to 0.95)×t is easily obtained, and the perpenducularity of the dowel section side surface is enhanced.Type: ApplicationFiled: December 25, 2006Publication date: January 22, 2009Inventors: Hirokazu Sasaki, Naofumi Nakamura, Shigeru Morikawa, Hideto Hashimoto, Takaaki Kimura, Yoshihiko Kawai
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Publication number: 20080311742Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.Type: ApplicationFiled: December 19, 2007Publication date: December 18, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadayoshi WATANABE, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu
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Publication number: 20080296775Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first dielectric film, a metal ring provided in the first dielectric film and the second dielectric film and configured to form a closed loop in a plan view, a first region surrounded by the metal ring in a plan view, a second region provided outside of the metal ring in a plan view, a plurality of via contacts provided in the first dielectric film in the first and second region, a plurality of wirings provided in the second dielectric film in the first and second region, and an air gap provided in the second dielectric film in the first region.Type: ApplicationFiled: December 6, 2007Publication date: December 4, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Noriaki Matsunaga, Yoshiaki Shimooka, Naofumi Nakamura
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Patent number: 7459391Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.Type: GrantFiled: August 22, 2005Date of Patent: December 2, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Takahiko Yoshizawa, Noriaki Matsunaga, Naofumi Nakamura
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Publication number: 20080261398Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.Type: ApplicationFiled: January 24, 2008Publication date: October 23, 2008Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Publication number: 20080122102Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.Type: ApplicationFiled: January 24, 2008Publication date: May 29, 2008Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Publication number: 20080090410Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.Type: ApplicationFiled: August 30, 2007Publication date: April 17, 2008Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Patent number: 7351656Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.Type: GrantFiled: January 20, 2006Date of Patent: April 1, 2008Assignee: Kabushiki Kaihsa ToshibaInventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Patent number: 7339256Abstract: A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.Type: GrantFiled: October 28, 2004Date of Patent: March 4, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Naofumi Nakamura, Noriaki Matsunaga, Sachiyo Ito, Masahiko Hasunuma, Takeshi Nishioka
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Patent number: 7169697Abstract: Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the wiring layer equal to the first wiring structure and including a second plug and a second wiring formed on the second plug, wherein the upper surface of the first wiring is positioned higher than the upper surface of the second wiring, and the lower surface of the first wiring is positioned flush with or lower than the upper surface of the second wiring. The present invention also provides a method of manufacturing the particular semiconductor device.Type: GrantFiled: November 9, 2004Date of Patent: January 30, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Makoto Sekine, Naofumi Nakamura