Abstract: An air-conditioning apparatus includes configured to, when a cooling operation mode is changed into one of multiple dehumidifying operation modes, select the one of the multiple dehumidifying operation modes on the basis of a value of a sensible heat ratio difference ?SHF that is a difference between a target sensible heat ratio acquired from an indoor temperature detected by an indoor temperature sensor, a target indoor temperature, and target indoor humidity and a theoretical minimum possible sensible heat ratio acquired from enthalpy of an indoor air, enthalpy of blown air from the indoor unit when relative humidity is 100%, and enthalpy of sensible heat.

Abstract: A reciprocal square root for a radix of x is calculated when S[j] represents the partial result obtained after j iterations of calculation, W[j], a residual, and P[j], the product of an operand X and the S[j]. Firstly, appropriate values are set to the initial values S[0], W[0], and P[0]. Secondly, n iterations of calculations from j=0 to n?1 are performed. One calculation includes selecting a reciprocal square root digit qj+1 from the digit set {?a, . . . , ?1, 0, 1, . . . , a}, and calculating a recurrence equation of the S[j], i.e., S[j+1]:=S[j]+qj+1r?j?1, a recurrence equation of the W[j], i.e., W[j+1]:=rW[j]?(2P[j]+Xqj+1r?j?1)qj+1, and a recurrence equation of the P[j], i.e., P[j+1]:=P[j]+Xqj+1r?j?1.

Abstract: A computing method for accelerating the iterations of modular multiplications is provided. In a newly defined image, variables U and V in a residue system are transformed to X=U·R mod M and Y=V·R mod M, and a modular multiplication U·V mod M is replaced with X·Y·R?1 mod M=U·V·R mod M. If R=rm where m is an integer that satisfies m<n, the multiplier U is transformed as X=U·rm mod M, and the multiplicand Y is transformed as Y=V·rm mod M. That is, X and Y are the images of U and V. The modular multiplication U·V mod M is replaced with X·Y·r?m mod M. In this manner, the parameter m is introduced to enable splitting of the multiplier Y into two parts of an upper part YH and a lower part YL and then process the two parts in parallel.

Abstract: A reciprocal square root for a radix of x is calculated when S[j] represents the partial result obtained after j iterations of calculation, W[j], a residual, and P[j], the product of an operand X and the S[j]. Firstly, appropriate values are set to the initial values S[0], W[0], and P[0]. Secondly, n iterations of calculations from j=0 to n−1 are performed. One calculation includes selecting a reciprocal square root digit qj+1 from the digit set {−a, . . . , −1, 0, 1, . . . , a}, and calculating a recurrence equation of the S[j], i.e., S[j+1]:=S[j]+qj+1r−j−1, a recurrence equation of the W[j], i.e., W[j+1]:=rW[j]−(2P[j]+Xqj+1r−j−1) qj+1, and a recurrence equation of the P[j], i.e.

Abstract: This an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers.

Abstract: This invention discloses an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers.

Abstract: An arithmetic processor cable of performing successive multiplication operations at high speeds is described in which the resultant product, internally represented as a carry-save or signed-digit expression, may be directly input in that form as the multiplier for the next successive multiplication operation. Additionally, a multiplier recoder circuit is provided which recodes the binary multiplier, in the form of a carry-save or signed-digit expression into a radix 4 signed-digit number, in order to further increase the operating speed.

Abstract: An arithmetic processor is disclosed for performing arithmetic operations utilizing an arithmetic operand represented by a signed digit expression having a plurality of digits which may have a positive, zero or negative value.

Abstract: A high speed arithmetic processor and adder circuitry thereof are disclosed in which carry (borrow) propagation is never more than one digit. Addition (or subtraction) are performed by: (a) determining an intermediate carry (or borrow) at the i-th order position and an intermediate sum (or difference) at the i-th order position from the addend (or subtrahend) and the augend (or minuend) and (b) determining the sum (or difference) of the intermediate sum (or difference) at the i-th order position and the intermediate carry (or borrow) at the (i-1)-th or next-lower-order position. Logic equations, truth tables and circuitry are disclosed for implementing several embodiments of the invention.

Abstract: A high speed processor including a multiplier is disclosed. The multiplier includes a multiplier recorder circuit which may record multipliers in groups of digits, and intermediate partial product generators which generate partial products from the recorded digits and a multiplicand. Addition/subtraction is then carried out on the intermediate partial products generated by the partial product generators. The processor may operate using signed digit expressions.