Patents by Inventor Naofumi Tsuchiya

Naofumi Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130075243
    Abstract: A switch device includes: a switch; an operation section disposed to face the switch; a first resilient section that is deformed by first pressing force derived from the operation section; and a second resilient section that is brought into contact with the switch by the deformation of the first resilient section, and is deformed to activate the switch by second pressing force greater than the first pressing force.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 28, 2013
    Applicant: Sony Corporation
    Inventors: Naofumi Tsuchiya, Makoto Koizumi, Hiroyuki Ono
  • Patent number: 8319317
    Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 27, 2012
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Katsuyuki Seki, Naofumi Tsuchiya, Akira Suzuki, Kikuo Okada
  • Patent number: 8148788
    Abstract: The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N? type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: April 3, 2012
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Akira Suzuki, Naofumi Tsuchiya, Koujiro Kameyama
  • Publication number: 20100052090
    Abstract: The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N? type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.
    Type: Application
    Filed: August 10, 2009
    Publication date: March 4, 2010
    Applicants: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., SANYO Electric Co., Ltd
    Inventors: Akira Suzuki, Naofumi Tsuchiya, Koujiro Kameyama
  • Publication number: 20090309193
    Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 17, 2009
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.
    Inventors: Katsuyuki SEKI, Naofumi TSUCHIYA, Akira SUZUKI, Kikuo OKADA
  • Patent number: 5915179
    Abstract: In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: June 22, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroki Etou, Kazunori Ohno, Takaaki Saito, Naofumi Tsuchiya, Toshinari Utsumi