Abstract: In a first-in-first-out register device positioned intermediately between an address calculation circuit and an operation execution circuit, both of which are individually operable in pipeline fashions, a stage number is varied from one to another in a register unit having a plurality of register stages, in consideration of an execution time which is necessary for a bus access operation carried out in response to a read instruction and which is variable. A maximum usable stage number is determined by a pointer control circuit in response to the variable execution time and is compared with an actual stage number, which is sent from a detector and which indicates an actual stage of the register unit. As a result, the register unit is controlled, so that the actual stage does not exceed the maximum usable stage.

Abstract: A data transfer apparatus comprises first and second memories each having a plurality of sectors each having the storage capacity of each sector in a storage disk. First and second memory access circuits are respectively associated with the first and second memories for successively specifying sectors of the associated one of the memories, writing data from the disk into the specified sectors and reading a copy of data from the associated one of the memories onto the system bus. A read/write control circuit controls the first and second memories to alternately operate in read and write modes when data is transferred between the disk and a system bus and causes one of the first and second memories to operate in a read mode when an error is detected in the transferred data.