Abstract: An operational amplifier includes a differential input stage that amplifies a differential input signal to generate an intermediate signal; an amplification stage including an output transistor that is connected between an output terminal and a fixed voltage line, and is driven according to the intermediate signal; and an assist circuit, wherein the assist circuit includes: a first transistor connected in parallel with the output transistor; and a drive circuit that drives the first transistor according to a gate voltage of the output transistor.

Abstract: A first current mirror circuit is provided between a first transistor and a power supply line to return a current that flows to the first transistor. A second current mirror circuit returns an output current from the first current mirror circuit, and generates a starting current. An inverter has an input connected to a node, and an output connected to a control terminal of the first transistor. A first current source generates a first current when a power supply voltage has exceeded a first threshold value. A third current mirror circuit draws a current proportional to the first current from an input side of the second current mirror circuit. A second current source supplies a second current to the node when the power supply voltage has exceeded a second threshold value.

Abstract: Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.

Abstract: Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.

Abstract: A first current mirror circuit is provided between a first transistor and a power supply line to return a current that flows to the first transistor. A second current mirror circuit returns an output current from the first current mirror circuit, and generates a starting current. An inverter has an input connected to a node, and an output connected to a control terminal of the first transistor. A first current source generates a first current when a power supply voltage has exceeded a first threshold value. A third current mirror circuit draws a current proportional to the first current from an input side of the second current mirror circuit. A second current source supplies a second current to the node when the power supply voltage has exceeded a second threshold value.

Abstract: A MEMS microphone includes: a glass substrate including an opening portion; a membrane provided on the glass substrate so as to cover the opening portion and including a first conductive layer; and a backplate provided above the membrane via a cavity, including a plurality of through holes through which sound waves pass, and including a second conductive layer. The first conductive layer is made of a metal or a conductive oxide. The second conductive layer is made of a metal or a conductive oxide.

Abstract: There is provided a chopper stabilized amplifier with an input bias current reduced. The chopper stabilized amplifier includes a main amplifier and a correction circuit. The correction circuit includes a second gm amplifier of a full differential type. A first selector and the second gm amplifier are coupled to each other without DC blocking capacitors. The differential input state of the second gm amplifier is configured with a depletion-type transistor.

Abstract: An operational amplifier includes a gain boost circuit. The gain boost circuit includes a first differential gm amplifier of a first stage, and a second differential gm amplifier of a post stage. Phase compensation capacitors are provided between inputs and outputs of a system of the second differential gm amplifier.

Abstract: A first transistor and a second transistor have control terminals coupled to each other. A current mirror circuit supplies a current having the same amount as that of a current Iref flowing through a first path including the second transistor to a second path including the first transistor and supplies a current having a predetermined number of times m of a current amount of the current Iref of the first path to a third path separate from the second path. The third transistor and a fourth transistor are provided on the third path. The third transistor has a source coupled to one end of the first transistor, and the fourth transistor has a gate coupled to a gate of the third transistor. A resistor is provided between a source of the fourth transistor and one end of the second transistor.

Abstract: A sample hold circuit includes at least one capacitor CS and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal VGN of the NMOS transistor is adjusted to a voltage level VREG lower than a power supply voltage VDD of a chip on which the CMOS switch is integrated.

Abstract: An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.

Abstract: A first transistor and a second transistor have control terminals coupled to each other. A current mirror circuit supplies a current having the same amount as that of a current Iref flowing through a first path including the second transistor to a second path including the first transistor and supplies a current having a predetermined number of times m of a current amount of the current Iref of the first path to a third path separate from the second path. The third transistor and a fourth transistor are provided on the third path. The third transistor has a source coupled to one end of the first transistor, and the fourth transistor has a gate coupled to a gate of the third transistor. A resistor is provided between a source of the fourth transistor and one end of the second transistor.

Abstract: A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.

Abstract: There is provided a chopper stabilized amplifier with an input bias current reduced. The chopper stabilized amplifier includes a main amplifier and a correction circuit. The correction circuit includes a second gm amplifier of a full differential type. A first selector and the second gm amplifier are coupled to each other without DC blocking capacitors. The differential input state of the second gm amplifier is configured with a depletion-type transistor.

Abstract: An operational amplifier includes a gain boost circuit. The gain boost circuit includes a first differential gm amplifier of a first stage, and a second differential gm amplifier of a post stage. Phase compensation capacitors are provided between inputs and outputs of a system of the second differential gm amplifier.

Abstract: A sample hold circuit includes at least one capacitor CS and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal VGN of the NMOS transistor is adjusted to a voltage level VREG lower than a power supply voltage VDD of a chip on which the CMOS switch is integrated.

Abstract: A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.

Abstract: An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.

Abstract: A main amplifier generates an output signal SOUT according to a difference between first and second voltages VP and VN. A first gm amplifier is arranged as a differential input stage. A second, fully differential, gm amplifier amplifies a voltage difference between its non-inverting and inverting input terminals, and outputs a differential current signal I3N/I3P via its inverting and non-inverting output terminals. An integrator integrates a differential input current I4P/I4N input via its non-inverting and inverting input terminals, and samples and holds the signal every predetermined period, to generate a differential voltage signal. A first selector is arranged as an upstream stage of the second gm amplifier, and outputs the differential input signal without change or otherwise after swapping. A second selector is arranged as a downstream stage of the second gm amplifier, and outputs the signal I3N/I3P output from the second gm amplifier without change or otherwise after swapping.

Abstract: A main amplifier generates an output signal SOUT according to a difference between first and second voltages VP and VN. A first gm amplifier is arranged as a differential input stage. A second, fully differential, gm amplifier amplifies a voltage difference between its non-inverting and inverting input terminals, and outputs a differential current signal I3N/I3P via its inverting and non-inverting output terminals. An integrator integrates a differential input current I4P/I4N input via its non-inverting and inverting input terminals, and samples and holds the signal every predetermined period, to generate a differential voltage signal. A first selector is arranged as an upstream stage of the second gm amplifier, and outputs the differential input signal without change or otherwise after swapping. A second selector is arranged as a downstream stage of the second gm amplifier, and outputs the signal I3N/I3P output from the second gm amplifier without change or otherwise after swapping.