Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Abstract: A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Abstract: The present invention relates to a circuit mounting unit that can prevent a voltage drop and noise occurrence due to current inflow at the time of a hot insertion or withdrawal operation without mounting a capacitor with large capacitance on the side of a main unit. The circuit mounting unit includes a first voltage control unit that controls to increase gradually a voltage supplied to a load voltage converter from the main unit side to a predetermined voltage when the circuit mounting unit is exchangeably inserted into or pulled out of the main unit without halting electric power supplied from the main unit. The circuit mounting unit is mounted onto a printed wiring board on which various elements such as ICs and LSIs are previously mounted to form a predetermined circuit.