Patents by Inventor Naohisa Okumura
Naohisa Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10490485Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.Type: GrantFiled: June 20, 2018Date of Patent: November 26, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa Okumura, Yasuhisa Shintoku, Tetsuya Kurosawa, Hiroaki Kishi
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Patent number: 10204891Abstract: According to one embodiment, a semiconductor module includes a first semiconductor element, a second semiconductor element, a first light emitting element and a second light emitting element. The first semiconductor element is provided with a first light receiving circuit and a first output circuit. The second semiconductor element is provided with a second light receiving circuit and a second output circuit. The first light emitting element is electrically connected to the second output circuit and mounted on the first semiconductor element such that first light emitted from the first light emitting element is received by the first light receiving circuit. The second light emitting element is electrically connected to the first output circuit and mounted on the second semiconductor element such that second light emitted from the second light emitting element is received by the second light receiving circuit.Type: GrantFiled: March 16, 2017Date of Patent: February 12, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Naohisa Okumura, Daijo Chida, Hiroaki Kishi, Isao Ogawa, Masaru Koseki
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Publication number: 20180331019Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.Type: ApplicationFiled: June 20, 2018Publication date: November 15, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa OKUMURA, Yasuhisa SHINTOKU, Tetsuya KUROSAWA, Hiroaki KISHI
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Patent number: 10026677Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.Type: GrantFiled: August 31, 2016Date of Patent: July 17, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa Okumura, Yasuhisa Shintoku, Tetsuya Kurosawa, Hiroaki Kishi
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Publication number: 20170250124Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.Type: ApplicationFiled: August 31, 2016Publication date: August 31, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa OKUMURA, Yasuhisa SHINTOKU, Tetsuya KUROSAWA, Hiroaki KISHI
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Publication number: 20170186738Abstract: According to one embodiment, a semiconductor module includes a first semiconductor element, a second semiconductor element, a first light emitting element and a second light emitting element. The first semiconductor element is provided with a first light receiving circuit and a first output circuit. The second semiconductor element is provided with a second light receiving circuit and a second output circuit. The first light emitting element is electrically connected to the second output circuit and mounted on the first semiconductor element such that first light emitted from the first light emitting element is received by the first light receiving circuit. The second light emitting element is electrically connected to the first output circuit and mounted on the second semiconductor element such that second light emitted from the second light emitting element is received by the second light receiving circuit.Type: ApplicationFiled: March 16, 2017Publication date: June 29, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Naohisa OKUMURA, Daijo CHIDA, Hiroaki KISHI, Isao OGAWA, Masaru KOSEKI
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Patent number: 9633984Abstract: According to one embodiment, a semiconductor module includes a first semiconductor element, a second semiconductor element, a first light emitting element and a second light emitting element. The first semiconductor element is provided with a first light receiving circuit and a first output circuit. The second semiconductor element is provided with a second light receiving circuit and a second output circuit. The first light emitting element is electrically connected to the second output circuit and mounted on the first semiconductor element such that first light emitted from the first light emitting element is received by the first light receiving circuit. The second light emitting element is electrically connected to the first output circuit and mounted on the second semiconductor element such that second light emitted from the second light emitting element is received by the second light receiving circuit.Type: GrantFiled: March 4, 2016Date of Patent: April 25, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Naohisa Okumura, Daijo Chida, Hiroaki Kishi, Isao Ogawa, Masaru Koseki
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Publication number: 20160268240Abstract: According to one embodiment, a semiconductor module includes a first semiconductor element, a second semiconductor element, a first light emitting element and a second light emitting element. The first semiconductor element is provided with a first light receiving circuit and a first output circuit. The second semiconductor element is provided with a second light receiving circuit and a second output circuit. The first light emitting element is electrically connected to the second output circuit and mounted on the first semiconductor element such that first light emitted from the first light emitting element is received by the first light receiving circuit. The second light emitting element is electrically connected to the first output circuit and mounted on the second semiconductor element such that second light emitted from the second light emitting element is received by the second light receiving circuit.Type: ApplicationFiled: March 4, 2016Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Naohisa OKUMURA, Daijo CHIDA, Hiroaki KISHI, Isao OGAWA, Masaru KOSEKI
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Patent number: 9236329Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.Type: GrantFiled: March 5, 2013Date of Patent: January 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhide Doi, Soichi Homma, Katsuyoshi Watanabe, Taku Nishiyama, Takeshi Ikuta, Naohisa Okumura
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Patent number: 9165870Abstract: According to the embodiment, a semiconductor storage device includes an organic substrate, a semiconductor memory chip, a lead frame, and a resin mold section. The lead frame includes an adhering portion. The organic substrate is singulated to have a shape in which a portion in which the organic substrate does not overlap with the placing portion is larger than a portion in which the organic substrate overlaps with the placing portion, in plan view. The lead frame further includes a first extending portion in the adhering portion that extends to a surface different from a surface of the resin mold section on a side of an insertion direction.Type: GrantFiled: June 24, 2011Date of Patent: October 20, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Ishii, Naohisa Okumura, Taku Nishiyama
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Patent number: 9033248Abstract: According to one embodiment, a semiconductor storage device is provided with a memory chip including a storage circuit, a controller chip that controls a memory chip, and a substrate having a first surface and a second surface opposing one another, on the first surface of which the controller chip is mounted. Further, the semiconductor storage device is provided with an external connection terminal formed on the second surface of the substrate, and resin that encapsulates the memory chip, the controller chip, and the substrate, includes a third surface and a fourth surface opposing one another, and has a predetermined mark directly printed only on the fourth surface that is adjacent to the second surface of the substrate.Type: GrantFiled: July 20, 2012Date of Patent: May 19, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hidetoshi Suzuki, Yuichi Hotta, Yuji Shimoda, Yuuji Ogawa, Taku Nishiyama, Tadanobu Okubo, Junichi Onodera, Takeshi Ikuta, Naohisa Okumura, Katsuyoshi Watanabe, Kazuhide Doi
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Publication number: 20140070381Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.Type: ApplicationFiled: March 5, 2013Publication date: March 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhide DOI, Soichi HOMMA, Katsuyoshi WATANABE, Taku NISHIYAMA, Takeshi IKUTA, Naohisa OKUMURA
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Patent number: 8575738Abstract: In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.Type: GrantFiled: February 29, 2012Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhide Doi, Naohisa Okumura, Taku Nishiyama, Katsuyoshi Watanabe, Takeshi Ikuta
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Publication number: 20130186960Abstract: According to one embodiment, a semiconductor storage device is provided with a memory chip including a storage circuit, a controller chip that controls a memory chip, and a substrate having a first surface and a second surface opposing one another, on the first surface of which the controller chip is mounted. Further, the semiconductor storage device is provided with an external connection terminal formed on the second surface of the substrate, and resin that encapsulates the memory chip, the controller chip, and the substrate, includes a third surface and a fourth surface opposing one another, and has a predetermined mark directly printed only on the fourth surface that is adjacent to the second surface of the substrate.Type: ApplicationFiled: July 20, 2012Publication date: July 25, 2013Inventors: Hidetoshi SUZUKI, Yuichi Hotta, Yuji Shimoda, Yuuji Ogawa, Taku Nishiyama, Tadanobu Okubo, Junichi Onodera, Takeshi Ikuta, Naohisa Okumura, Katsuyoshi Watanabe, Kazuhide Doi
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Patent number: 8395268Abstract: A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element gType: GrantFiled: June 29, 2011Date of Patent: March 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Tetsuya Yamamoto, Naohisa Okumura
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Patent number: 8314478Abstract: According to one embodiment, a semiconductor memory device including an organic substrate with an external connection terminal and a semiconductor memory chip. The semiconductor memory device further includes a lead frame having a bonded portion and an installation portion. It further includes a resin mold for sealing the semiconductor memory chip. The lead frame is provided with a plurality of extensions at least from one of the installation portion and the bonded portion, in a way of extending at least to two or more sides of the resin mold.Type: GrantFiled: March 18, 2011Date of Patent: November 20, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Ishii, Naohisa Okumura
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Patent number: 8288855Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.Type: GrantFiled: November 3, 2011Date of Patent: October 16, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Naohisa Okumura, Kiyokazu Okada
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Publication number: 20120241933Abstract: In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.Type: ApplicationFiled: February 29, 2012Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhide Doi, Naohisa Okumura, Taku Nishiyama, Katsuyoshi Watanabe, Takeshi Ikuta
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Patent number: 8274141Abstract: A semiconductor memory card includes a wiring board having an outer shape where a cut-out portion is provided at a first long-edge. A second surface of the wiring board includes connection pads disposed along a portion except the cut-out portion of the first long-edge. A memory device is mounted on the second surface of the wiring board. The memory device includes electrode pads arranged along a long-edge positioning in a vicinity of the first long-edge of the wiring board, and one-sidedly disposed so as to correspond to disposed positions of the connection pads. A controller device is stacked on the memory device.Type: GrantFiled: March 9, 2009Date of Patent: September 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Tetsuya Yamamoto, Naohisa Okumura, Takuya Futatsuyama
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Publication number: 20120043671Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.Type: ApplicationFiled: November 3, 2011Publication date: February 23, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taku NISHIYAMA, Naohisa Okumura, Kiyokazu Okada