Abstract: An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs.

Abstract: A multiprocessor system can reduce a broadcast for cache memory consistency control with memory access from an I/O device. The multiprocessor system is provided with a cache memory identifier or an owner tag, and a block length table for recording a memory write block length of the I/O device. The cache memory identifier records that the cache has an exclusive copy. The owner tag records that there is no cache memory having an exclusive copy. If there is an exclusive copy during read through the I/O device, a read request is issued to both a cache holding the copy and a memory. If it is recorded that the copy is not present, data are directly read from the memory. Moreover, when a write block length is recorded in the block length table during write, whole blocks are collected to issue a request for invalidation from the cache and the request is directly written to the memory after the invalidation is completed.

Abstract: Disclosed are a virtual computer system and method, wherein computer resources are automatically and optimally allocated to logical partitions according to loads to be accomplished by operating systems in the logical partitions and setting information based on a knowledge of workloads that run on the operating systems. Load measuring modules are installed on the operating systems in order to measure the loads to be accomplished by the operating systems. A manager designates the knowledge concerning the workloads on the operating systems through a user interface. An adaptive control module determines the alalocation ratios of the computer resources relative to the logical partitions according to the loads and the settings, and issues an allocation varying instruction to a hypervisor so as to thus instruct variation of allocations.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: A virtual computer system including a reallocation means, in which a plurality of LPAR are operated by logically dividing physical resources composing a physical computer exclusively or in time dividing manner so as to dynamically change reallocation of physical resources among each of LPARs. Based on load conditions measured by an application or an OS of each LPAR, physical resource allocation to each LPAR is determined, thereby conducting reallocation of LPAR.

Abstract: A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: A cache memory unit that preferentially stores specific lines into the cache memory, according to the program nature, dynamically changes the priority ranks of lines, and increases the cache memory hit rate, in which: the lines to be accessed by a processor are divided into groups and definitions of the groups are set in a group definition table; policy whereby to store lines belonging to the groups into the cache memory is set in a policy table; and storing lines into the cache memory is executed, according to the group definitions and the policy of storing set in the above tables.

Abstract: A multiprocessor system can reduce a broadcast for cache memory consistency control with memory access from an I/O device. The multiprocessor system is provided with a cache memory identifier or an owner tag, and a block length table for recording a memory write block length of the I/O device. The cache memory identifier has an exclusive copy. The owner tag records that there is no cache memory having an exclusive copy. If there is an exclusive copy during read through the I/O device, a read request is issued to both a cache holding the copy and a memory. If it is recorded that the copy is not present, data are directly read from the memory. Moreover, when a write block length is recorded in the block length table during write, whole blocks are collected to issue a request for invalidation from the cache and the request is directly written to the memory after the invalidation is completed.

Abstract: In a bus or switch coupled system having a plurality of processor modules and a memory module, the memory module is provided with a unit for returning a write completion acknowledgement (WRITE_ACK) to a write requesting processor module. If a processor module PM1 is under execution of write-back of a cache line upon arrival of a cache coherence check (CCC) issued from a processor module with a cache miss of the cache line, an “INVALID” signal is returned to the CCC issued processor module PMO after a write completion acknowledgment from the memory module is confirmed and the cache line is invalidated. After confirming the “INVALID” signals from other processor modules, the CCC issued processor module issues a READ transaction to the memory module to obtain correct latest data reflecting the write-back data of the processor module.

Abstract: A multiprocessor system that performs processing of transactions issued consecutively by Posted Write with a device on an I/O bus as a transaction source or target. If one of a series of transactions with a device on some I/O bus of a plurality of I/O buses in the system as source is retried at a target node, the subsequent transactions from that I/O bus also are retried, and the sending unit of the source node reissues these transactions. At that time, a header flag is added to the first of a series of reissued transactions. At the transaction processing unit of the target node, if processing is impossible, a retry flag is set with the bit corresponding to the I/O bus of the issuing source in the retry flag register and a retry is returned to the source, and henceforth retries are returned also when receiving subsequent transactions with the same I/O bus as issuing source. When the resent transaction added the header flag is received, whether or not processing is possible is judged again.

Abstract: A cache status report sum up for use in a multiprocessor system having a plurality of processor units each having a processor and a cache memory and a plurality of memory units. The cache status report sum up apparatus sums up cache coherency check results indicating statuses of the cache memories without limiting the number of memory access requests requiring cache coherency checks that can be overlapped when the memory access requests requiring cache coherency checks are executed in an overlapping manner. The cache status report sum up apparatus is provided between the processor units and the memory units and sums up cache coherency check results sent by cache status reporting apparatus included in each processor unit. The cache status reporting apparatus responds to a memory access request requiring a cache coherency check.

Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.

Abstract: A processor for a multiprocessor system, such as a parallel processor system, connected to a network has a sending unit and a receiving unit for transferring and receiving data to and from the network as well as a receive cache and a main cache. When data is received from the network, it is determined whether a hit or miss occurs to the main cache and receive cache, respectively. If a hit to the receive cache occurs, then the receive cache controller stores the data directly in the receive cache as it is received. When a hit to the main cache occurs, an intercache transfer is executed for transferring the hit block in the main cache to the receive cache so that the data can be stored in the receive cache. When an instruction processor requests access to data held in the receive cache, the data is retrieved to the instruction processor and at the same time transferred to a main cache.

Abstract: A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs.

Abstract: Information indicative of whether each processor unit caches data which belongs to each of the plural areas of the main memory larger than a cache line is stored in the multicast table. The destinations of a coherent processing request which should be sent to other processor units are limited by the information stored in this table. The interconnection network broadcasts the request to the limited destinations. When the processor unit of the destination of this processing request sends back a cache status of the data designated by the request, it also sends back the caching status in the processor unit concerning a specific memory area which includes the data. Depending on this send back, the request source processor unit renews a portion relating to the destination processor unit within the caching status concerning that specific memory area stored in the processor unit.

Abstract: In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

Abstract: A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.

Abstract: A sorting method used with a distributed database having a plurality of first processors for holding partial records of a database that is divided into a plurality of portions and a host processor for accessing to each of the first processors. The method comprises the steps of: assigning a plurality of sections into which the distribution range of key values of records of the database is partitioned to a plurality of second processors in the first processors, and information for representing storage positions of the records to the second processors to which the sections of the key values, to which the records belong, are assigned; and sorting the plurality of key values, which have been received, in the second processors to produce key tables in which the information for representing the storage positions of the records which has been received is registrated together with the sorted key values, as the sorting result.

Abstract: In a method of transferring packets in a network for a parallel processor system handling a one-to-one transfer packet to be transferred from a processor to another processor and a broadcast packet to be transferred from a processor to a plurality of other processors, a transfer request of a broadcast packet is preferentially selected and a check is made to detect whether or not a plurality of processors specified as receivers are in a state in which the packet can be received. The broadcast packet is transferred to the processors found to be in the state in which the packet can be received. The packet transfer is delayed for the other processors in a state in which the packet cannot be received. Namely, only when the state of the processors is changed to the state in which the packet can be received, the broadcast packet is transferred thereto.