Patents by Inventor Naoki Kanda
Naoki Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230330720Abstract: A washing device includes a temperature adjuster that is configured to at least one of: heat a first fluid for washing a container for storing a substrate; or cool a second fluid for washing the container, so as to supply the first fluid having a first temperature and the second fluid having a second temperature lower than the first temperature; and a washer that is configured to: supply the first fluid to a first surface of the container to heat and wash the container; and supply the second fluid to a second surface of the container to cool and wash the container.Type: ApplicationFiled: February 28, 2023Publication date: October 19, 2023Applicant: Kioxia CorporationInventors: Naoki KANDA, Hiroshi TOMITA, Tooru MIKAMI
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Publication number: 20230274953Abstract: A substrate treatment device includes an EFEM unit, a cleaning and drying unit, and at least one load port unit, and the cleaning and drying unit includes a wafer holding mechanism, a transfer arm, a cleaning liquid supply nozzle, and a gas supply nozzle. The EFEM unit includes a transfer robot and a transfer arm capable of transferring a wafer between a load port unit of the at least one load port unit and the cleaning and drying unit, and the cleaning and drying unit is coupled to the EFEM unit in series with the load port unit.Type: ApplicationFiled: December 29, 2022Publication date: August 31, 2023Applicant: KIOXIA CORPORATIONInventors: Tooru MIKAMI, Naoki KANDA, Hiroshi TOMITA
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Publication number: 20230257273Abstract: Provided are porous spherical silica particles whose oil absorption is suppressed while the porous spherical silica particles have a large specific surface area; and a method for manufacturing such spherical silica particles. According to the present invention, provided are spherical silica particles whose specific surface area obtained by employing a BET method is 300 m2/g or more, total pore volume is 0.3 ml/g or less, and oil absorption is 50 ml/100 g or less, the spherical silica particles obtained by subjecting silica gel particles obtained by employing a sol-gel method, for example, in which an alkali silicate is emulsified and coagulated, to only drying at a low temperature without subjecting the silica gel particles to calcination at a high temperature; and a method for manufacturing such spherical silica particles.Type: ApplicationFiled: June 9, 2021Publication date: August 17, 2023Applicant: TAYCA CORPORATIONInventors: Naoki KANDA, Daisuke OOSAKI, Toru TANAKA
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Publication number: 20210315781Abstract: Provided is an inorganic powder composite used for a water-in-oil type fine dispersion system which is excellent in emulsification and emulsification stability. The inorganic powder composite includes: an inorganic powder; and a first hydrophobic treatment agent, a second hydrophobic treatment agent, and a hydrophilic treatment agent, which cover at least one part of a surface of the inorganic powder, the first hydrophobic treatment agent is a silicon compound, the second hydrophobic treatment agent is a fatty acid, and the hydrophilic treatment agent is hydrous silica.Type: ApplicationFiled: October 18, 2019Publication date: October 14, 2021Applicant: TAYCA CORPORATIONInventors: Shunsuke MITO, Kenji KAYAHARA, Naoki KANDA
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Patent number: 8293257Abstract: An oily dispersion of an inorganic microparticle oxide powder that exhibits excellent texture has superior compatibility with other cosmetic material components. The oily dispersion contains only two components of a dispersion medium and a surface-treated inorganic microparticle oxide powder, wherein the dispersion medium is an oil, the surface-treated inorganic microparticle oxide powder is a powder surface-treated with branched fatty acid containing isostearic acid as a primary constituent component or a metal salt containing isostearic acid as a primary constituent component at an amount of 1 to 30% by weight with respect to the powder as a base material, and the surface-treated inorganic microparticle oxide powder has a solid concentration of 25% by weight or more and a viscosity of 2,000 mPa·s or less at 25° C. in the preparation of the oily dispersion.Type: GrantFiled: December 28, 2011Date of Patent: October 23, 2012Assignee: Tayca CorporationInventors: Kazunori Yagi, Naoki Kanda
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Publication number: 20120100196Abstract: An oily dispersion of an inorganic microparticle oxide powder that exhibits excellent texture has superior compatibility with other cosmetic material components. The oily dispersion contains only two components of a dispersion medium and a surface-treated inorganic microparticle oxide powder, wherein the dispersion medium is an oil, the surface-treated inorganic microparticle oxide powder is a powder surface-treated with branched fatty acid containing isostearic acid as a primary constituent component or a metal salt containing isostearic acid as a primary constituent component at an amount of 1 to 30% by weight with respect to the powder as a base material, and the surface-treated inorganic microparticle oxide powder has a solid concentration of 25% by weight or more and a viscosity of 2,000 mPa·s or less at 25° C. in the preparation of the oily dispersion.Type: ApplicationFiled: December 28, 2011Publication date: April 26, 2012Applicant: TAYCA CORPORATIONInventors: Kazunori YAGI, Naoki KANDA
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Patent number: 7614145Abstract: A curable resin composition layer (3) containing an insulating resin and a curing agent is formed on the surface of an inner layer board having an electrical insulating layer (1) with a conductor circuit (2) formed on the surface, so as to cover said conductor circuit. A compound (4) having a structure capable of coordinating to metal atoms or metal ions is brought into contact with the surface of the curable resin composition layer. An electrical insulating layer (7) is formed by curing the curable resin composition layer. A metallic thin film layer (8) is formed on the surface of the electrical insulating layer. A conductor circuit (9) is formed on the surface of the electrical insulating layer utilizing the metallic thin film layer. A multilayer circuit board is manufactured through these steps.Type: GrantFiled: September 4, 2002Date of Patent: November 10, 2009Assignee: Zeon CorporationInventors: Yasuhiro Wakizaka, Koichi Ikeda, Naoki Kanda
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Patent number: 6905928Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: GrantFiled: May 9, 2002Date of Patent: June 14, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Patent number: 6870224Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: GrantFiled: August 15, 2003Date of Patent: March 22, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Publication number: 20040237295Abstract: A curable resin composition layer (3) containing an insulating resin and a curing agent is formed on the surface of an inner layer board having an electrical insulating layer (1) with a conductor circuit (2) formed on the surface, so as to cover said conductor circuit. A compound (4) having a structure capable of coordinating to metal atoms or metal ions is brought into contact with the surface of the curable resin composition layer. An electrical insulating layer (7) is formed by curing the curable resin composition layer. A metallic thin film layer (8) is formed on the surface of the electrical insulating layer. A conductor circuit (9) is formed on the surface of the electrical insulating layer utilizing the metallic thin film layer. A multilayer circuit board is manufactured through these steps.Type: ApplicationFiled: February 27, 2004Publication date: December 2, 2004Inventors: Yasuhiro Wakizaka, Koichi Ikeda, Naoki Kanda
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Publication number: 20040145001Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: ApplicationFiled: August 15, 2003Publication date: July 29, 2004Applicant: Hitachi, Ltd., IncorporationInventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Publication number: 20040051139Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: ApplicationFiled: August 15, 2003Publication date: March 18, 2004Applicant: Hitachi, LtdInventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Publication number: 20030183901Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: ApplicationFiled: May 9, 2002Publication date: October 2, 2003Applicant: Hitachi, Ltd.Inventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Publication number: 20020190295Abstract: Bit lines BL of a DRAM that are narrowed to 0.1 &mgr;m or less are made of two-layered conductive films, in which a W (tungsten) film is deposited on a WN (tungsten nitride) film. For bit lines BL, fewer W atoms diffuse across the interface between the W film and the WN film, within crystal grains, and at grain boundaries of the W film, and no tensile stress exists in the W film. Therefore, high-temperature thermal processing in the capacitor formation process does not cause wiring breaks even when the width of the bit lines BL is narrowed to 0.1 &mgr;m or less.Type: ApplicationFiled: August 1, 2002Publication date: December 19, 2002Inventors: Masayuki Suzuki, Kentaro Yamada, Masashi Sahara, Takashi Nakajima, Naoki Kanda, Hidenori Suzuki, Yoshinori Matsumuro
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Patent number: 6429476Abstract: Bit lines BL of a DRAM that are narrowed to 0.1 &mgr;m or less are made of two-layered conductive films, in which a W (tungsten) film is deposited on a WN (tungsten nitride) film. For bit lines BL, fewer W atoms diffuse across the interface between the W film and the WN film, within crystal grains, and at grain boundaries of the W film, and no tensile stress exists in the W film. Therefore, high-temperature thermal processing in the capacitor formation process does not cause wiring breaks even when the width of the bit lines BL is narrowed to 0.1 &mgr;m or less.Type: GrantFiled: March 1, 2001Date of Patent: August 6, 2002Assignee: Hitachi, Ltd.Inventors: Masayuki Suzuki, Kentaro Yamada, Masashi Sahara, Takashi Nakajima, Naoki Kanda, Hidenori Suzuki, Yoshinori Matsumuro
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Publication number: 20010050386Abstract: Bit lines BL of the DRAM that are narrowed to 0.1 &mgr;m or less are made of two-layered conductive films, in which a W (tungsten) film is deposited on a WN (tungsten nitride) film. For bit lines BL, fewer W atoms diffuse across the interface between the W film and the WN film, within crystal grains, and at grain boundaries of the W film, and no tensile stress exists in the W film. Therefore, high-temperature thermal processing in the capacitor formation process does not cause wiring breaks even when the width of bit lines BL is narrowed to 0.1 &mgr;m or less.Type: ApplicationFiled: March 1, 2001Publication date: December 13, 2001Inventors: Masayuki Suzuki, Kentaro Yamada, Masashi Sahara, Takashi Nakajima, Naoki Kanda, Hidenori Suzuki, Yoshinori Matsumuro
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Patent number: 6326512Abstract: Disclosed is a method of producing an optically active &bgr;-hydroxy sulfonic acid compound comprising hydrogenating a &bgr;-keto sulfonic acid compound represented by formula 1: where R1 represents an alkyl or a phenyl group, which may be substituted, and R2 represents sodium or an alkyl group, in an acidic solvent, in the presence of an asymmetric catalyst comprising a complex of bivalent Ru, having 2,2′-bis(diphenylphosphino)-1,1′-binaphthyl as a ligand, to produce a compound represented by formula 2: where R1 and R2 are as defined above, and * designates an asymmetric carbon atom.Type: GrantFiled: June 1, 2000Date of Patent: December 4, 2001Assignee: President of Nagoya UniversityInventors: Masato Kitamura, Masahiro Yoshimura, Naoki Kanda, Ryoji Noyori