Abstract: A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.

Abstract: A semiconductor memory device, including a first memory cell having a first gate electrode, a first diffusion layer, and a second diffusion layer; a first contact layer connected to the first diffusion layer of the first memory cell; a second contact layer connected to the first contact layer; a second memory cell having a second gate electrode, a third diffusion layer and a fourth diffusion layer, the second gate electrode of the second memory cell electrically connected to the first gate electrode of the first memory cell, the first and second memory cells arranged in a direction perpendicular to the first bit line; and a conductive layer commonly connected to the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell, a height of the conductive layer substantially being coplanar with a height of the first contact layer.

Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Abstract: A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.

Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

Abstract: In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.

Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.

Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

Abstract: In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.

Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.

Abstract: In a semiconductor device having a contact structure, a semiconductor element is formed on the surface of a semiconductor substrate and an inter-level insulating film is formed on the entire surface. Then, an insulating film having a high etching selective ratio with respect to the inter-level insulating film is formed on the inter-level insulating film. After this, the thus formed insulating film is etched back and left behind only on the side wall of a stepped portion caused in the inter-level insulating film which defines a contact hole forming area. Then, a contact hole having an upper end portion formed in a forward tapered form is formed in the inter-level insulating film by use of a SAC technique using an insulating film left on the side wall of the stepped portion as the etching stopper.

Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.