Abstract: A pair of supply/drain pipes continuous with an actuator are respectively communicable with a pair of oil sumps respectively through an intermediation of a pair of extended paths. The pair of oil sumps is formed in a switch-spool insertion hole and enter a neutral state or a state of being selectively communicated with any one of respective pressure-oil paths and respective oil-return paths. A non-leak valve is provided over respective connection portions and between the pair of supply/drain pipes and the pair of extended paths. The non-leak valve is opened when an operation of a pump is started, is maintained to be opened during the operation of the pump, and is closed when the pump is out of operation.

Abstract: A data processing apparatus includes: a data input section for receiving input of a plurality discrete data arranged at predetermined time intervals; a first-derivative adding section for adding a first derivative to each input discrete data; using a plurality of the discrete data with the additional first derivative, when a difference between one or a plurality of discrete data interposed between two discrete data and a value on a curve passing through the two discrete data points generated on the basis of the two discrete data, the first derivative, and time interval information of the two discrete data is within an allowable error, a homogeneity/heterogeneity conversion section for obtaining a plurality of discrete data having heterogeneous time intervals and the additional first derivative by thinning one or a plurality of the discrete data interposed between the two discrete data; and a heterogeneous-data generation section for generating the heterogeneous data.

Abstract: A pair of supply/drain pipes (Y and Z) continuous with an actuator (2) are respectively communicable with a pair of oil sumps (A, B, C) and (F, G, H) each other respectively through an intermediation of a pair of extended paths (a and b), the pair of oil sumps (A, B, C) and (F, G, H) being formed in a switch-spool insertion hole (7) and entering a neutral state or a state of being selectively communicated with any one of respective pressure-oil paths (S and V) and respective oil-return paths (Q and W). A non-leak valve (12) is provided over respective connection portions (I and J) and (K and L) between the pair of supply/drain pipes (Y and Z) and the pair of extended paths (a and b), the non-leak valve (12) being opened when an operation of a pump (P) is started, being maintained to be opened during the operation of the pump (P), and being closed when the pump (P) is out of operation.

Abstract: A data processing apparatus includes: a data input section for receiving input of a plurality discrete data arranged at predetermined time intervals; a first-derivative adding section for adding a first derivative to each input discrete data; using a plurality of the discrete data with the additional first derivative, when a difference between one or a plurality of discrete data interposed between two discrete data and a value on a curve passing through the two discrete data points generated on the basis of the two discrete data, the first derivative, and time interval information of the two discrete data is within an allowable error, a homogeneity/heterogeneity conversion section for obtaining a plurality of discrete data having heterogeneous time intervals and the additional first derivative by thinning one or a plurality of the discrete data interposed between the two discrete data; and a heterogeneous-data generation section for generating the heterogeneous data.

Abstract: A chroma-decoder 1 has two SRCs 17 and 21. The first SRC 17 performs down-conversion, changing the sampling rate of a composite video signal sampled with a system clock signal Cs to the sampling rate (14.3 MHz) of an NTSC signal. The signal generated by the SRC 17 is output in synchronism with the system clock signal Cs. The signal is then divided into a luminance signal Y and a color-difference signal C, which are subjected to chroma decoding. The second SRC 21 performs down-conversion, changing the sampling rate of the luminance signal and color-difference signal of the NTSC signal to the sampling rate (13.5 MHz) of an ITU-R601 standard.

Abstract: A chroma-decoder 1 has two SRCs 17 and 21. The first SRC 17 performs down-conversion, changing the sampling rate of a composite video signal sampled with a system clock signal Cs to the sampling rate (14.3 MHz) of an NTSC signal. The signal generated by the SRC 17 is output in synchronism with the system clock signal Cs. The signal is then divided into a luminance signal Y and a color-difference signal C, which are subjected to chroma decoding. The second SRC 21 performs down-conversion, changing the sampling rate of the luminance signal and color-difference signal of the NTSC signal to the sampling rate (13.5 MHz) of an ITU-R601 standard.

Abstract: The present invention provides an 8-bit D/A converter comprising a first current supply for outputting a current representing input digital luminance signal data and a second current supply for outputting a predetermined current except during pulse periods of a synchronization signal Sync supplied along with the digital luminance signal data wherein the sum of the current generated by the first current supply in accordance with the digital luminance signal data and the predetermined current generated by the second current supply in accordance with the synchronization signal Sync is output.Consequently an analog luminance signal from a D/A converter with a tone expression thereof improved by effectively utilizing the dynamic range of the D/A converter is obtained.

Abstract: A D/A converter comprises a bias circuit including a series circuit of a drain-source of a bias FET and a bias resistor connected between a power source terminal and a reference potential point, the bias circuit includes a negative feedback amplifier to which a reference voltage is supplied, a digital to analog converting section includes a plurality of constant-current source FETs having a current value substantially equal to the current value of the bias FET of the bias circuit, and includes a plurality of current switches for selectively supplying currents of the constant-current source FETs to an output terminal in response to a digital input signal. An output resistor with resistance value Ro is connected to the output terminal to produce an analog output voltage across the output resistor and the resistance of the bias resistor is varied so as to adjust the full scale voltage across the output resistor while maintaining the relationship that the resistance value of the bias resistor is selected by (2.