Patents by Inventor Naoki KUNESHITA

Naoki KUNESHITA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072152
    Abstract: A method of manufacturing a semiconductor device includes: forming a first trench from an upper surface side of a semiconductor substrate; burying the first trench with an insulated gate electrode structure; forming a base region at an upper part of the semiconductor substrate so as to be in contact with the first trench; forming a first main electrode region at an upper part of the base region so as to be in contact with the first trench; forming a second trench by removing a part of the first main electrode region; implanting first impurity ions entirely into a side wall surface of the second trench from a diagonally upper side; implanting second impurity ions into a bottom surface of the second trench to form a contact region at a bottom of the second trench; and forming a second main electrode region on a bottom surface side of the semiconductor substrate.
    Type: Application
    Filed: June 26, 2023
    Publication date: February 29, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Naoki KUNESHITA, Masayuki MOMOSE, Ryutaro HAMASAKI
  • Publication number: 20230187221
    Abstract: Provided is a semiconductor device manufacturing method including a process of annealing a semiconductor wafer in a state in which a supported portion on a lower surface of the semiconductor wafer is supported by using a supporting portion, wherein the supported portion includes one or a plurality of supporting portions and the supporting portion includes one or a plurality of supporting portions, the method comprising: forming impurity regions including a first impurity in a region which is overlapped with the supported portion in a top view and which is apart from an edge of the semiconductor wafer; annealing the semiconductor wafer in a state in which the lower surface of the semiconductor wafer is supported by the supporting portion; and removing the impurity regions by removing a region including the lower surface of the semiconductor wafer.
    Type: Application
    Filed: October 20, 2022
    Publication date: June 15, 2023
    Inventors: Takane YAMADA, Masayuki MOMOSE, Naoki KUNESHITA
  • Publication number: 20230178377
    Abstract: A first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type, gate trenches, a gate insulating film, gate electrodes, and an interlayer insulating film are formed. Next, a contact hole that penetrates through the interlayer insulating film and reaches the first semiconductor region is formed, and in a surface layer of the first semiconductor region exposed at a bottom of the contact hole, a third semiconductor region of the second conductivity type is formed by an ion implantation using, as a mask, a polymer formed herewith; and after the ion implantation, the polymer is removed. Next, a fourth semiconductor region of the second conductivity type, a first electrode, and a second electrode are formed.
    Type: Application
    Filed: October 31, 2022
    Publication date: June 8, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Naoki KUNESHITA, Makoto ENDOU, Atsushi YOSHIMOTO
  • Patent number: 10446409
    Abstract: An interlayer insulating film is dry etched using a CHF3 gas and by using, as a mask, a resist film having a first opening and a second opening that is wider than the first opening, thereby forming a first contact hole of a predetermined depth in the first opening and forming a second contact hole in the second opening. The gas in a furnace is switched to a C4F8 gas and the first contact hole is embedded with a polymer by the C4F8 gas. The gas in the furnace is switched to a CHF3 gas. With the first contact hole protected by the polymer, the interlayer insulating film is dry etched using the same resist film as a mask, making a depth of the second contact hole a predetermined depth deeper than that of the first contact hole. Thereafter, the resist film and the polymer are removed.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kuneshita
  • Publication number: 20190067029
    Abstract: An interlayer insulating film is dry etched using a CHF3 gas and by using, as a mask, a resist film having a first opening and a second opening that is wider than the first opening, thereby forming a first contact hole of a predetermined depth in the first opening and forming a second contact hole in the second opening. The gas in a furnace is switched to a C4F8 gas and the first contact hole is embedded with a polymer by the C4F8 gas. The gas in the furnace is switched to a CHF3 gas. With the first contact hole protected by the polymer, the interlayer insulating film is dry etched using the same resist film as a mask, making a depth of the second contact hole a predetermined depth deeper than that of the first contact hole. Thereafter, the resist film and the polymer are removed.
    Type: Application
    Filed: June 27, 2018
    Publication date: February 28, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki KUNESHITA