Patents by Inventor Naoki Mitsuishi
Naoki Mitsuishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10540305Abstract: A semiconductor device is provided that can process various events while suppressing complication of logical configuration. The semiconductor device includes a central processing unit, a plurality of functional blocks, and an event controller. Each functional block includes an interrupt factor detection unit that detects an interrupt factor and outputs an event processing request based on the interrupt factor, an event ID input unit that receives an input of an event ID outputted from the event controller, an event response specification unit that determines whether or not the inputted event ID is an event ID that requires response and, when the inputted event ID is an event ID that requires response, specifies response content corresponding to the inputted event ID, and an event response processing unit that performs event response processing based on the specified response content.Type: GrantFiled: November 19, 2017Date of Patent: January 21, 2020Assignee: Renesas Electronics CorporationInventor: Naoki Mitsuishi
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Patent number: 10409749Abstract: An SCI can perform transmission only or reception only, however, it is necessary to reset the SCI when transmission and reception is switched to transmission only or to reception only. A semiconductor device includes an interface circuit which performs a sequential communication of transmit or receive according to a synchronous clock. The interface circuit includes a register to specify an operation enabled state which is at least one of a transmit state and a receive state, and a mode control circuit to change at least one mode of transmit or receive in the operation enabled state.Type: GrantFiled: May 2, 2016Date of Patent: September 10, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoki Mitsuishi, Seiji Ikari
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Semiconductor device for generating a clock by partially enabling or disabling a source clock signal
Patent number: 10359829Abstract: It is to provide a technique capable of controlling the throughput and the power consumption of a semiconductor device at a desired ratio. A semiconductor device includes a clock generation circuit that generates a clock signal and a data processing unit that receives the clock signal. The clock generation circuit includes an oscillator that generates a source clock signal, an output circuit that outputs a clock signal with the source clock signal enabled, and a control circuit having a setting circuit in which the data processing unit sets the ratio of the enable. The semiconductor device can change the frequency of the clock signal by partially permitting or prohibiting the source clock signal in time.Type: GrantFiled: March 24, 2016Date of Patent: July 23, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Naoki Mitsuishi -
Patent number: 10223304Abstract: A microcomputer includes a central processing unit (CPU) and a data transfer controller (DTC). The data transfer controller (DTC) reads out data transfer information including transfer mode information from a storage device (RAM) or the like. The data transfer controller (DTC) analyzes the transfer mode information to change at least one of a transfer source address, a transfer destination address, the number of transfer operations, and data transfer information that is used next.Type: GrantFiled: October 25, 2014Date of Patent: March 5, 2019Assignee: Renesas Electronics CorporationInventors: Yasuhiko Takahashi, Seiji Ikari, Naoki Mitsuishi
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Publication number: 20180322079Abstract: An object is to obtain output data corresponding to input data by referring to table data by a semiconductor apparatus having a simple configuration. An MCU includes a DTC for transferring data from a source address region to a destination address region based on data transfer information in response to a startup request. The DTC performs an operation on second source address information based on data that has been read from first source address information, performs reading based on a result of the operation, and writes read data based on destination address information.Type: ApplicationFiled: July 12, 2018Publication date: November 8, 2018Inventors: Naoki Mitsuishi, Seiji Ikari, Katsumasa Uchiyama
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Patent number: 10108469Abstract: A microcomputer includes a plurality of functional blocks that exchange information with each other. A nonvolatile memory can rewrite information stored therein and first data has been written therein in advance. A central processing unit processes information read from the nonvolatile memory or writes information to the nonvolatile memory. An abnormality detecting unit detects an abnormality in exchange of data between the plurality of functional blocks. A nonvolatile memory checking unit reads the first data from the nonvolatile memory when the abnormality detecting unit has detected an abnormality, compares the first data with second data indicating the content of the first data when written to the nonvolatile memory, and detects an abnormality in the nonvolatile memory when a result of the comparison shows that the first data is not identical to the second data.Type: GrantFiled: July 18, 2015Date of Patent: October 23, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Naoki Mitsuishi
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Patent number: 10102161Abstract: A microcomputer includes: a central processing unit (CPU); a data transfer apparatus (DTC); and a storage apparatus (RAM). The data transfer apparatus includes a plurality of register files each including a mode register storing the transfer mode information, an address register to which the address information is transferred, and a status register (SR) representing information that specifies the transfer information set. The data transfer apparatus checks the information of the status register, to determine whether to use the transfer information set held in the register files or to read the transfer information set from the storage apparatus and to rewrite a prescribed one of the register files. The data transfer apparatus performs data transfer based on the transfer information set stored in one of the register files.Type: GrantFiled: July 20, 2015Date of Patent: October 16, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoki Mitsuishi, Seiji Ikari
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Patent number: 10049063Abstract: An object is to obtain output data corresponding to input data by referring to table data by a semiconductor apparatus having a simple configuration. An MCU includes a DTC for transferring data from a source address region to a destination address region based on data transfer information in response to a startup request. The DTC performs an operation on second source address information based on data that has been read from first source address information, performs reading based on a result of the operation, and writes read data based on destination address information.Type: GrantFiled: December 30, 2014Date of Patent: August 14, 2018Assignee: Renesas Electronics CorporationInventors: Naoki Mitsuishi, Seiji Ikari, Katsumasa Uchiyama
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Publication number: 20180181508Abstract: A semiconductor device is provided that can process various events while suppressing complication of logical configuration. The semiconductor device includes a central processing unit, a plurality of functional blocks, and an event controller. Each functional block includes an interrupt factor detection unit that detects an interrupt factor and outputs an event processing request based on the interrupt factor, an event ID input unit that receives an input of an event ID outputted from the event controller, an event response specification unit that determines whether or not the inputted event ID is an event ID that requires response and, when the inputted event ID is an event ID that requires response, specifies response content corresponding to the inputted event ID, and an event response processing unit that performs event response processing based on the specified response content.Type: ApplicationFiled: November 19, 2017Publication date: June 28, 2018Inventor: Naoki MITSUISHI
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Patent number: 9977753Abstract: A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.Type: GrantFiled: April 10, 2017Date of Patent: May 22, 2018Assignee: Renesas Electronics CorporationInventors: Naoki Mitsuishi, Seiji Ikari
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Publication number: 20170212853Abstract: A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Inventors: Naoki MITSUISHI, Seiji IKARI
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Patent number: 9652229Abstract: A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.Type: GrantFiled: December 18, 2014Date of Patent: May 16, 2017Assignee: Renesas Electronics CorporationInventors: Naoki Mitsuishi, Seiji Ikari
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Publication number: 20170019142Abstract: An SCI can perform transmission only or reception only, however, it is necessary to reset the SCI when transmission and reception is switched to transmission only or to reception only. A semiconductor device includes an interface circuit which performs a sequential communication of transmit or receive according to a synchronous clock. The interface circuit includes a register to specify an operation enabled state which is at least one of a transmit state and a receive state, and a mode control circuit to change at least one mode of transmit or receive in the operation enabled state.Type: ApplicationFiled: May 2, 2016Publication date: January 19, 2017Inventors: Naoki MITSUISHI, Seiji IKARI
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Publication number: 20160334831Abstract: It is to provide a technique capable of controlling the throughput and the power consumption of a semiconductor device at a desired ratio. A semiconductor device includes a clock generation circuit that generates a clock signal and a data processing unit that receives the clock signal. The clock generation circuit includes an oscillator that generates a source clock signal, an output circuit that outputs a clock signal with the source clock signal enabled, and a control circuit having a setting circuit in which the data processing unit sets the ratio of the enable. The semiconductor device can change the frequency of the clock signal by partially permitting or prohibiting the source clock signal in time.Type: ApplicationFiled: March 24, 2016Publication date: November 17, 2016Inventor: Naoki MITSUISHI
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Publication number: 20160048392Abstract: A microcomputer includes: a central processing unit (CPU); a data transfer apparatus (DTC); and a storage apparatus (RAM). The data transfer apparatus includes a plurality of register files each including a mode register storing the transfer mode information, an address register to which the address information is transferred, and a status register (SR) representing information that specifies the transfer information set. The data transfer apparatus checks the information of the status register, to determine whether to use the transfer information set held in the register files or to read the transfer information set from the storage apparatus and to rewrite a prescribed one of the register files. The data transfer apparatus performs data transfer based on the transfer information set stored in one of the register files.Type: ApplicationFiled: July 20, 2015Publication date: February 18, 2016Inventors: Naoki MITSUISHI, Seiji Ikari
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Publication number: 20160041860Abstract: A microcomputer includes a plurality of functional blocks that exchange information with each other. A nonvolatile memory can rewrite information stored therein and first data has been written therein in advance. A central processing unit processes information read from the nonvolatile memory or writes information to the nonvolatile memory. An abnormality detecting unit detects an abnormality in exchange of data between the plurality of functional blocks. A nonvolatile memory checking unit reads the first data from the nonvolatile memory when the abnormality detecting unit has detected an abnormality, compares the first data with second data indicating the content of the first data when written to the nonvolatile memory, and detects an abnormality in the nonvolatile memory when a result of the comparison shows that the first data is not identical to the second data.Type: ApplicationFiled: July 18, 2015Publication date: February 11, 2016Inventor: Naoki MITSUISHI
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Publication number: 20150193367Abstract: An object is to obtain output data corresponding to input data by referring to table data by a semiconductor apparatus having a simple configuration. An MCU includes a DTC for transferring data from a source address region to a destination address region based on data transfer information in response to a startup request. The DTC performs an operation on second source address information based on data that has been read from first source address information, performs reading based on a result of the operation, and writes read data based on destination address information.Type: ApplicationFiled: December 30, 2014Publication date: July 9, 2015Inventors: Naoki Mitsuishi, Seiji Ikari, Katsumasa Uchiyama
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Publication number: 20150178003Abstract: A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.Type: ApplicationFiled: December 18, 2014Publication date: June 25, 2015Inventors: Naoki MITSUISHI, Seiji IKARI
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Publication number: 20150127867Abstract: A microcomputer includes a central processing unit (CPU) and a data transfer controller (DTC). The data transfer controller (DTC) reads out data transfer information including transfer mode information from a storage device (RAM) or the like. The data transfer controller (DTC) analyzes the transfer mode information to change at least one of a transfer source address, a transfer destination address, the number of transfer operations, and data transfer information that is used next.Type: ApplicationFiled: October 25, 2014Publication date: May 7, 2015Inventors: Yasuhiko TAKAHASHI, Seiji IKARI, Naoki MITSUISHI
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Patent number: 8645742Abstract: Serial communication with a bit rate close to a required bit rate can be performed, regardless of the frequency of an operation clock. A semiconductor device includes a serial communication interface that operates according to a certain operation clock. The serial communication interface is provided with a baud rate generator that generates a basic clock for counting the operation clock to define the unit transfer time based on the count, and a transmission/reception controller for performing control of transmission and reception according to the generated basic clock. Further, the serial communication interface is provided with a bit rate modulator capable of realizing a desired bit rate by partially masking supply of the operation clock to the baud rate generator, and thereby serial communication with a bit rate close to a required bit rate is realized.Type: GrantFiled: November 20, 2010Date of Patent: February 4, 2014Assignee: Renesas Electronics CorporationInventor: Naoki Mitsuishi