Abstract: In a zero-phase current detecting apparatus, a feedback loop is made up of a pulse generating unit, a current detecting unit, a peak detecting unit, an adding unit, and a current regulating unit. The adding unit outputs a difference between a target value and a peak value detected by the peak detecting unit. A zero-phase current is detected based on the difference output from the adding unit as a result of regulation of the peak value so as to be the target value in the adding unit.

Abstract: An interconnection inverter device includes a pair of capacitors connected in series to a pair of direct-current buses each connecting a direct-current power supply and the inverter; an opening/closing unit connected to either one of the pair of direct-current buses; voltage monitor units that monitor terminal voltages of the pair of capacitors respectively; and a controller that controls opening or closing of the opening/closing unit based on monitor voltages detected by the voltage monitor units.

Abstract: A first booster circuit and a second booster circuit include input capacitors, reactors, diodes, switch elements, and output capacitors, and are arranged to be symmetric to each other on a positive side and a negative side. The reactors are magnetically coupled to each other. With such configuration, the switch elements are on/off controlled simultaneously based on terminal voltages of the input capacitors and the output capacitors.

Abstract: A grounding wire from a commercial power system is connected to a series-connection end of a series connection between two capacitors connected in series between a positive electrode and a negative electrode. A current detector monitors an output current of an inverter unit in which four switching elements and two diodes convert voltages at both ends of the series circuit of the capacitors at three levels. An operation control circuit controls a generation of a PWM signal to be applied to the four switching elements, to minimize a difference between a current value detected by the current detector and a target current value.

Abstract: An interconnection inverter device includes a pair of capacitors connected in series to a pair of direct-current buses each connecting a direct-current power supply and the inverter; an opening/closing unit connected to either one of the pair of direct-current buses; voltage monitor units that monitor terminal voltages of the pair of capacitors respectively; and a controller that controls opening or closing of the opening/closing unit based on monitor voltages detected by the voltage monitor units.

Abstract: Disclosed is a method of readily removing particles from a stage, that is, a stage particle removing method for removing particles from a stage that holds a planar workpiece. A resin film is placed on the stage, and collected from the stage. The resin film is coated over at least one surface of the planar workpiece such as a semiconductor wafer or glass substrate. The resin film is brought into contact with the stage. The resin film may not be coated over the planar workpiece itself but may be coated over a dedicated planar piece shaped similarly to the planar workpiece, for example, a thin metallic plate that is very smooth. The used resin film is peeled off from the planar workpiece or dedicated planar piece, and the resin film is coated again. Thus, the planar workpiece or dedicated planar piece can be reused.

Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 &mgr;m or smaller, and can be cut off without causing damage to a layer beneath the fuses.

Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 &mgr;m or smaller, and can be cut off without causing damage to a layer beneath the fuses.

Abstract: The present invention is a method of charged particle beam exposure wherein an area of an exposure pattern is exposed by irradiating a sample with a charged particle beam while moving said sample, comprising: a step of generating speed data including the speed distribution in a direction of movement of the sample in accordance with secondary data which is generated from a pattern data including at least data of the exposure pattern and data of an exposure position, and includes at least density information of the exposure pattern; and a step of irradiating the sample with the charged particle beam in accordance with the pattern data while being moved at variable speed in accordance with the speed data. According to the invention, the through-put is improved very much without any defect of the exposure.

Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 .mu.m or smaller, and can be cut off without causing damage to a layer beneath the fuses.

Abstract: The present invention provides a coating phosphor comprising phosphor particles, heat resistive coating films which coat the phosphor particles and moisture proof coating films which coat the heat resistive coating films.

Abstract: A system for generating control data comprises an imput component having a movable member, a position detecting component for detecting a position of the movable member and for outputting a position signal, a random access memory component for storing control data therein, a writing component for writing the control data in the random access memory component, an analog to digital converting component for converting the position signal to a digital position signal and for outputting the digital position signal as a read address, a reading component for reading out the control data from the read address of the random access memory component, and output component for outputting the control data read out from the random access memory component.

Abstract: In a slow motion video generation apparatus; successive fields of an input video signal are stored in field stores, a spatial interpolator spatially interpolates between lines of a field selected from those stored in the field stores to produce a spatially interpolated video signal, a temporal filter carries out temporal interpolation between a pair of fields of the same interlace polarity selected from those stored in the field stores to produce a temporally filtered video signal, a combining device selectively receives the spatially and temporally interpolated video signals, and a movement indicator compares the fields stored in the field stores to detect whether or not there is local movement in the picture represented by the stored fields and controls the combining device so that the output signal is substantially wholly constituted by the temporally interpolated video signal in picture areas where substantially no movement is detected and is substantially wholly constituted by the spatially interpolated

Abstract: A digital signal processing circuit for carrying out a series of processings for a digital signal having a signal effective interval and blanking interval such as a video signal. Operation control data added to the blanking interval of the input digital signal controls the signal processings of a plurality of signal processing blocks, so that the circuit construction can be simplified and complicated signal processings can be achieved.